[llvm] [AArch64][CodeGen] Add patterns for small negative VScale const (PR #89607)
Paul Walker via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 23 05:42:11 PDT 2024
================
@@ -2583,6 +2583,27 @@ let Predicates = [HasSVEorSME] in {
sub_32)>;
}
+ // Add NoUseScalarIncVL to avoid affecting for patterns with UseScalarIncVL
+ let Predicates = [NoUseScalarIncVL] in {
+ def : Pat<(add GPR64:$op, (vscale (sve_rdvl_imm i32:$imm))),
+ (ADDXrs GPR64:$op, (RDVLI_XI $imm), 0)>;
----------------
paulwalker-arm wrote:
I agree there's a code difference but it's not bad is it? They're both result in two instructions, with the first being invariant and thus hoist able.
https://github.com/llvm/llvm-project/pull/89607
More information about the llvm-commits
mailing list