[llvm] [AArch64][SelectionDAG] Lower multiplication by a constant to shl+add+shl+add (PR #89532)

[Eli Friedman via llvm-commits]

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@@ -17632,6 +17651,10 @@ static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
         SDValue MVal = Add(Shl(N0, ShiftM1), N0);
         return Add(Shl(MVal, ShiftN1), MVal);
       }
+    } else if (Subtarget->hasALULSLFast() &&
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efriedma-quic wrote:

I think the the limit for ALULSLFast supposed to be 4?  Not sure where 3 came from; maybe some confusion with the old LSLFast for loads.

I'm a little concerned the structure of the nested if statements could miss some cases... is it possible for a number to pass both isPowPlusPlusConst and isPowPlusPlusOneConst?  Maybe we can restructure the code to just be a series of if statements with early returns, instead of if/else if/etc.?

https://github.com/llvm/llvm-project/pull/89532