[llvm] [Exegesis][RISCV] Add RISCV support for llvm-exegesis (PR #89047)

[via llvm-commits]

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@@ -524,7 +524,7 @@ class HLoad_r<bits<7> funct7, bits<5> funct5, string opcodestr>
 // Operands for stores are in the order srcreg, base, offset rather than
 // reflecting the order these fields are specified in the instruction
 // encoding.
-let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1, UseNamedOperandTable = 1 in {
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AnastasiyaChernikova wrote:

'UseNamedOperandTable = 1' builds a table that's used to find instruction operand by its name in td

https://github.com/llvm/llvm-project/pull/89047