[llvm] [RISC-V][ISel] Remove redundant czero.eqz like 'czero.eqz a0, a0, a0' (PR #90208)

[Zhijin Zeng via llvm-commits]

https://github.com/zengdage created https://github.com/llvm/llvm-project/pull/90208

In RISC-V ISel，the instruction `czero.eqz a0, a0, a0` is meaningless，I think it need to be removed. So I upload the patch to do this job.  When the condition is  `setcc falseValue, 0, seteq`,  the `select `instruction don't need to add a ` czero.eqz` instruciton.

>From 00e3511459ba865a8a69828ad222b1374d2321c1 Mon Sep 17 00:00:00 2001
From: Zhijin Zeng <zhijin.zeng at spacemit.com>
Date: Fri, 26 Apr 2024 20:50:13 +0800
Subject: [PATCH] [RISC-V][ISel] Remove redundant czero.eqz like 'czero.eqz a0,
 a0, a0'

Signed-off-by: Zhijin Zeng <zhijin.zeng at spacemit.com>
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 11 +++++
 llvm/test/CodeGen/RISCV/select.ll           | 55 +++++++++++++++++++++
 2 files changed, 66 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 769c465d56f984..422f6610ce8126 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7503,6 +7503,17 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
       return DAG.getNode(ISD::ADD, DL, VT, CMOV, RHSVal);
     }
 
+    // c = setcc f, 0, seteq
+    // (select c, t, f) -> (or f, (czero_nez t, f))
+    if (CondV.getOpcode() == ISD::SETCC &&
+        ISD::SETEQ == cast<CondCodeSDNode>(CondV.getOperand(2))->get()) {
+      SDValue LHS = CondV.getOperand(0);
+      SDValue RHS = CondV.getOperand(1);
+      if (isNullConstant(RHS) && LHS == FalseV)
+        return DAG.getNode(
+            ISD::OR, DL, VT, FalseV,
+            DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, TrueV, LHS));
+    }
     // (select c, t, f) -> (or (czero_eqz t, c), (czero_nez f, c))
     // Unless we have the short forward branch optimization.
     if (!Subtarget.hasConditionalMoveFusion())
diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll
index e07e52091e9e71..6efbbe0baf5375 100644
--- a/llvm/test/CodeGen/RISCV/select.ll
+++ b/llvm/test/CodeGen/RISCV/select.ll
@@ -1858,3 +1858,58 @@ define i32 @select_cst6(i1 zeroext %cond) {
   %ret = select i1 %cond, i32 2049, i32 2047
   ret i32 %ret
 }
+
+ at select_redundant_czero_eqz_data = global i32 0, align 4
+
+define void @select_redundant_czero_eqz(ptr %0, ptr %1) {
+; RV32IM-LABEL: select_redundant_czero_eqz:
+; RV32IM:       # %bb.0:
+; RV32IM-NEXT:    bnez a0, .LBB49_2
+; RV32IM-NEXT:  # %bb.1:
+; RV32IM-NEXT:    lui a0, %hi(select_redundant_czero_eqz_data)
+; RV32IM-NEXT:    addi a0, a0, %lo(select_redundant_czero_eqz_data)
+; RV32IM-NEXT:  .LBB49_2:
+; RV32IM-NEXT:    sw a0, 0(a1)
+; RV32IM-NEXT:    ret
+;
+; RV64IM-LABEL: select_redundant_czero_eqz:
+; RV64IM:       # %bb.0:
+; RV64IM-NEXT:    bnez a0, .LBB49_2
+; RV64IM-NEXT:  # %bb.1:
+; RV64IM-NEXT:    lui a0, %hi(select_redundant_czero_eqz_data)
+; RV64IM-NEXT:    addi a0, a0, %lo(select_redundant_czero_eqz_data)
+; RV64IM-NEXT:  .LBB49_2:
+; RV64IM-NEXT:    sd a0, 0(a1)
+; RV64IM-NEXT:    ret
+;
+; RV64IMXVTCONDOPS-LABEL: select_redundant_czero_eqz:
+; RV64IMXVTCONDOPS:       # %bb.0:
+; RV64IMXVTCONDOPS-NEXT:    lui a2, %hi(select_redundant_czero_eqz_data)
+; RV64IMXVTCONDOPS-NEXT:    addi a2, a2, %lo(select_redundant_czero_eqz_data)
+; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a2, a2, a0
+; RV64IMXVTCONDOPS-NEXT:    or a0, a0, a2
+; RV64IMXVTCONDOPS-NEXT:    sd a0, 0(a1)
+; RV64IMXVTCONDOPS-NEXT:    ret
+;
+; RV32IMZICOND-LABEL: select_redundant_czero_eqz:
+; RV32IMZICOND:       # %bb.0:
+; RV32IMZICOND-NEXT:    lui a2, %hi(select_redundant_czero_eqz_data)
+; RV32IMZICOND-NEXT:    addi a2, a2, %lo(select_redundant_czero_eqz_data)
+; RV32IMZICOND-NEXT:    czero.nez a2, a2, a0
+; RV32IMZICOND-NEXT:    or a0, a0, a2
+; RV32IMZICOND-NEXT:    sw a0, 0(a1)
+; RV32IMZICOND-NEXT:    ret
+;
+; RV64IMZICOND-LABEL: select_redundant_czero_eqz:
+; RV64IMZICOND:       # %bb.0:
+; RV64IMZICOND-NEXT:    lui a2, %hi(select_redundant_czero_eqz_data)
+; RV64IMZICOND-NEXT:    addi a2, a2, %lo(select_redundant_czero_eqz_data)
+; RV64IMZICOND-NEXT:    czero.nez a2, a2, a0
+; RV64IMZICOND-NEXT:    or a0, a0, a2
+; RV64IMZICOND-NEXT:    sd a0, 0(a1)
+; RV64IMZICOND-NEXT:    ret
+  %3 = icmp eq ptr %0, null
+  %4 = select i1 %3, ptr @select_redundant_czero_eqz_data, ptr %0
+  store ptr %4, ptr %1, align 8
+  ret void
+}