[llvm] [RISCV] Implement RISCVISD::SHL_ADD and move patterns into combine (PR #89263)

[Craig Topper via llvm-commits]

================
@@ -26,6 +26,12 @@
 // Operand and SDNode transformation definitions.
 //===----------------------------------------------------------------------===//
 
+def SDTIntShiftAddOp : SDTypeProfile<1, 3, [   // shl_add
+  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 3>, SDTCisInt<0>, SDTCisInt<2>,
+  SDTCisInt<3>
+]>;
+
+def riscv_shl_add    : SDNode<"RISCVISD::SHL_ADD"   , SDTIntShiftAddOp>;
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topperc wrote:

Formatting is weird on this line. I assume it was copied from below but the spacing wasn't updated.

https://github.com/llvm/llvm-project/pull/89263