[llvm] [RISCV] Remove SEW operand for load/store and SEW-aware pseudos (PR #90396)

[Pengcheng Wang via llvm-commits]

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@@ -191,6 +215,28 @@ static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
   return Desc.getNumOperands() - Offset;
 }
 
+static inline unsigned getLog2SEW(uint64_t TSFlags) {
+  return 3 + RISCVII::getVSEW(TSFlags);
+}
+
+static inline MachineOperand getSEWOp(const MachineInstr &MI) {
+  uint64_t TSFlags = MI.getDesc().TSFlags;
+  assert(hasSEW(TSFlags) && "The instruction doesn't have SEW value!");
+  if (hasSEWOp(TSFlags))
+    return MI.getOperand(getSEWOpNum(MI.getDesc()));
+
+  return MachineOperand::CreateImm(getLog2SEW(TSFlags));
+}
+
+static inline unsigned getLog2SEW(const MachineInstr &MI) {
+  uint64_t TSFlags = MI.getDesc().TSFlags;
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wangpc-pp wrote:

I thought about this before, but it seems to be silly because for the code path that `RISCVII::hasSEWOp` returns false, we will create an immediate operand and then extract the imm.

https://github.com/llvm/llvm-project/pull/90396