[llvm] 5dd46d9 - [RISCV] Fix off by 1 typo in decodeVMaskReg. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-04-26T12:10:24-07:00
New Revision: 5dd46d93fb9d7e7f8c9774433d60fd16dc659eb6

URL: https://github.com/llvm/llvm-project/commit/5dd46d93fb9d7e7f8c9774433d60fd16dc659eb6
DIFF: https://github.com/llvm/llvm-project/commit/5dd46d93fb9d7e7f8c9774433d60fd16dc659eb6.diff

LOG: [RISCV] Fix off by 1 typo in decodeVMaskReg. NFC

We're decoding a 1 bit field, but checked that the value was <= 2
instead of <= 1.

This isn't a functional change because the generated disassembler code
that calls this only extracts 1 bit.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 3cd6e743418355..497283ceea1e1a 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -258,9 +258,9 @@ static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo,
 static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo,
                                    uint64_t Address,
                                    const MCDisassembler *Decoder) {
-  if (RegNo > 2) {
+  if (RegNo >= 2)
     return MCDisassembler::Fail;
-  }
+
   MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister;
 
   Inst.addOperand(MCOperand::createReg(Reg));