[llvm] [ARM][AArch64] autogenerate header file for TargetParser from Target tablegen files (PR #88378)
Tomas Matheson via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 23 08:01:51 PDT 2024
https://github.com/tmatheson-arm updated https://github.com/llvm/llvm-project/pull/88378
>From 7d2968ebf35c343ecf6b2285d8ad69184af52721 Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Wed, 10 Apr 2024 13:17:15 +0100
Subject: [PATCH 1/5] [ARM] autogen ARMProcFamilyEnum/ARMArchEnum from ARM.td
This header is generated in TargetParser. These changes do not make use
of it in TargetParser itself, but future changes will.
The end goal is to share information between TargetParser and the
backend.
---
llvm/include/llvm/TargetParser/CMakeLists.txt | 5 ++
llvm/lib/Target/ARM/ARMSubtarget.cpp | 1 -
llvm/lib/Target/ARM/ARMSubtarget.h | 82 ++-----------------
llvm/lib/TargetParser/CMakeLists.txt | 1 +
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 67 +++++++++++++++
llvm/utils/TableGen/CMakeLists.txt | 1 +
6 files changed, 80 insertions(+), 77 deletions(-)
create mode 100644 llvm/utils/TableGen/ARMTargetDefEmitter.cpp
diff --git a/llvm/include/llvm/TargetParser/CMakeLists.txt b/llvm/include/llvm/TargetParser/CMakeLists.txt
index 7f080e01548c7c..725bcfbd6468ee 100644
--- a/llvm/include/llvm/TargetParser/CMakeLists.txt
+++ b/llvm/include/llvm/TargetParser/CMakeLists.txt
@@ -1,3 +1,8 @@
+set(LLVM_TARGET_DEFINITIONS ${PROJECT_SOURCE_DIR}/lib/Target/ARM/ARM.td)
+tablegen(LLVM ARMTargetParserDef.inc -gen-arm-target-def -I ${PROJECT_SOURCE_DIR}/lib/Target/ARM/)
+add_public_tablegen_target(ARMTargetParserTableGen)
+
set(LLVM_TARGET_DEFINITIONS ${PROJECT_SOURCE_DIR}/lib/Target/RISCV/RISCV.td)
tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def -I ${PROJECT_SOURCE_DIR}/lib/Target/RISCV/)
add_public_tablegen_target(RISCVTargetParserTableGen)
+
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 04ba20a17187b4..20543f63e496f1 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -293,7 +293,6 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
case CortexA78C:
case CortexA710:
case CortexR4:
- case CortexR4F:
case CortexR5:
case CortexR7:
case CortexM3:
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 497ae160fde281..3c07c91b9baad0 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -49,45 +49,9 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
protected:
enum ARMProcFamilyEnum {
Others,
-
- CortexA12,
- CortexA15,
- CortexA17,
- CortexA32,
- CortexA35,
- CortexA5,
- CortexA53,
- CortexA55,
- CortexA57,
- CortexA7,
- CortexA72,
- CortexA73,
- CortexA75,
- CortexA76,
- CortexA77,
- CortexA78,
- CortexA78AE,
- CortexA78C,
- CortexA710,
- CortexA8,
- CortexA9,
- CortexM3,
- CortexM7,
- CortexM52,
- CortexR4,
- CortexR4F,
- CortexR5,
- CortexR52,
- CortexR7,
- CortexX1,
- CortexX1C,
- Exynos,
- Krait,
- Kryo,
- NeoverseN1,
- NeoverseN2,
- NeoverseV1,
- Swift
+ #define ARM_PROCESSOR_FAMILY(ENUM) ENUM,
+ #include "llvm/TargetParser/ARMTargetParserDef.inc"
+ #undef ARM_PROCESSOR_FAMILY
};
enum ARMProcClassEnum {
None,
@@ -97,43 +61,9 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
RClass
};
enum ARMArchEnum {
- ARMv4,
- ARMv4t,
- ARMv5,
- ARMv5t,
- ARMv5te,
- ARMv5tej,
- ARMv6,
- ARMv6k,
- ARMv6kz,
- ARMv6m,
- ARMv6sm,
- ARMv6t2,
- ARMv7a,
- ARMv7em,
- ARMv7m,
- ARMv7r,
- ARMv7ve,
- ARMv81a,
- ARMv82a,
- ARMv83a,
- ARMv84a,
- ARMv85a,
- ARMv86a,
- ARMv87a,
- ARMv88a,
- ARMv89a,
- ARMv8a,
- ARMv8mBaseline,
- ARMv8mMainline,
- ARMv8r,
- ARMv81mMainline,
- ARMv9a,
- ARMv91a,
- ARMv92a,
- ARMv93a,
- ARMv94a,
- ARMv95a,
+ #define ARM_ARCHITECTURE(ENUM) ENUM,
+ #include "llvm/TargetParser/ARMTargetParserDef.inc"
+ #undef ARM_ARCHITECTURE
};
public:
diff --git a/llvm/lib/TargetParser/CMakeLists.txt b/llvm/lib/TargetParser/CMakeLists.txt
index da1e352b037338..742c87c20505f5 100644
--- a/llvm/lib/TargetParser/CMakeLists.txt
+++ b/llvm/lib/TargetParser/CMakeLists.txt
@@ -37,5 +37,6 @@ add_llvm_component_library(LLVMTargetParser
Support
DEPENDS
+ ARMTargetParserTableGen
RISCVTargetParserTableGen
)
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
new file mode 100644
index 00000000000000..5253d7225d5183
--- /dev/null
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -0,0 +1,67 @@
+//===- ARMTargetDefEmitter.cpp - Generate data about ARM Architectures ----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This tablegen backend exports information about CPUs, FPUs, architectures,
+// and features into a common format that can be used by both TargetParser and
+// the ARM backend.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ADT/StringSet.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/TableGenBackend.h"
+
+using namespace llvm;
+
+static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
+ OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n";
+
+ // Look through all SubtargetFeature defs with the given FieldName, and
+ // collect the set of all Values that that FieldName is set to.
+ auto gatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
+ llvm::StringSet<> Set;
+ for (const Record *Rec : RK.getAllDerivedDefinitions("SubtargetFeature")) {
+ if (Rec->getValueAsString("FieldName") == FieldName) {
+ Set.insert(Rec->getValueAsString("Value"));
+ }
+ }
+ return Set;
+ };
+
+ // The ARMProcFamilyEnum values are initialised by SubtargetFeature defs
+ // which set the ARMProcFamily field. We can generate the enum from these defs
+ // which look like this:
+ //
+ // def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
+ // "Cortex-A5 ARM processors", []>;
+ OS << "#ifndef ARM_PROCESSOR_FAMILY\n"
+ << "#define ARM_PROCESSOR_FAMILY(ENUM)\n"
+ << "#endif\n\n";
+ const StringSet<> ARMProcFamilyVals =
+ gatherSubtargetFeatureFieldValues("ARMProcFamily");
+ for (const StringRef &Family : ARMProcFamilyVals.keys()) {
+ OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n";
+ }
+ OS << "\n#undef ARM_PROCESSOR_FAMILY\n";
+ OS << "\n";
+
+ OS << "#ifndef ARM_ARCHITECTURE\n"
+ << "#define ARM_ARCHITECTURE(ENUM)\n"
+ << "#endif\n\n";
+ // This should correspond to instances of the Architecture tablegen class.
+ const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch");
+ for (const StringRef &Arch : ARMArchVals.keys()) {
+ OS << "ARM_ARCHITECTURE(" << Arch << ")\n";
+ }
+ OS << "\n#undef ARM_ARCHITECTURE\n";
+ OS << "\n";
+}
+
+static TableGen::Emitter::Opt
+ X("gen-arm-target-def", EmitARMTargetDef,
+ "Generate the ARM Architecture information header.");
diff --git a/llvm/utils/TableGen/CMakeLists.txt b/llvm/utils/TableGen/CMakeLists.txt
index 577aeded4be72c..7b54a9059b680e 100644
--- a/llvm/utils/TableGen/CMakeLists.txt
+++ b/llvm/utils/TableGen/CMakeLists.txt
@@ -32,6 +32,7 @@ set(LLVM_LINK_COMPONENTS
add_tablegen(llvm-tblgen LLVM
DESTINATION "${LLVM_TOOLS_INSTALL_DIR}"
EXPORT LLVM
+ ARMTargetDefEmitter.cpp
AsmMatcherEmitter.cpp
AsmWriterEmitter.cpp
Attributes.cpp
>From 3201b36560fdf01b3706d9b248aefc5c1a12bea0 Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Wed, 10 Apr 2024 13:33:56 +0100
Subject: [PATCH 2/5] [AArch64] autogen ARMProcFamilyEnum from AArch64.td
---
llvm/include/llvm/TargetParser/CMakeLists.txt | 4 ++
llvm/lib/Target/AArch64/AArch64Subtarget.h | 58 +------------------
llvm/lib/TargetParser/CMakeLists.txt | 1 +
llvm/utils/TableGen/CMakeLists.txt | 2 +-
4 files changed, 9 insertions(+), 56 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/CMakeLists.txt b/llvm/include/llvm/TargetParser/CMakeLists.txt
index 725bcfbd6468ee..f89d4eb5ea1638 100644
--- a/llvm/include/llvm/TargetParser/CMakeLists.txt
+++ b/llvm/include/llvm/TargetParser/CMakeLists.txt
@@ -2,6 +2,10 @@ set(LLVM_TARGET_DEFINITIONS ${PROJECT_SOURCE_DIR}/lib/Target/ARM/ARM.td)
tablegen(LLVM ARMTargetParserDef.inc -gen-arm-target-def -I ${PROJECT_SOURCE_DIR}/lib/Target/ARM/)
add_public_tablegen_target(ARMTargetParserTableGen)
+set(LLVM_TARGET_DEFINITIONS ${PROJECT_SOURCE_DIR}/lib/Target/AArch64/AArch64.td)
+tablegen(LLVM AArch64TargetParserDef.inc -gen-arm-target-def -I ${PROJECT_SOURCE_DIR}/lib/Target/AArch64/)
+add_public_tablegen_target(AArch64TargetParserTableGen)
+
set(LLVM_TARGET_DEFINITIONS ${PROJECT_SOURCE_DIR}/lib/Target/RISCV/RISCV.td)
tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def -I ${PROJECT_SOURCE_DIR}/lib/Target/RISCV/)
add_public_tablegen_target(RISCVTargetParserTableGen)
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 95bef7a76bcab7..8ff5f9076f53b9 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -39,61 +39,9 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
public:
enum ARMProcFamilyEnum : uint8_t {
Others,
- A64FX,
- Ampere1,
- Ampere1A,
- Ampere1B,
- AppleA7,
- AppleA10,
- AppleA11,
- AppleA12,
- AppleA13,
- AppleA14,
- AppleA15,
- AppleA16,
- AppleA17,
- Carmel,
- CortexA35,
- CortexA53,
- CortexA55,
- CortexA510,
- CortexA520,
- CortexA57,
- CortexA65,
- CortexA72,
- CortexA73,
- CortexA75,
- CortexA76,
- CortexA77,
- CortexA78,
- CortexA78AE,
- CortexA78C,
- CortexA710,
- CortexA715,
- CortexA720,
- CortexR82,
- CortexX1,
- CortexX1C,
- CortexX2,
- CortexX3,
- CortexX4,
- ExynosM3,
- Falkor,
- Kryo,
- NeoverseE1,
- NeoverseN1,
- NeoverseN2,
- Neoverse512TVB,
- NeoverseV1,
- NeoverseV2,
- Saphira,
- ThunderX2T99,
- ThunderX,
- ThunderXT81,
- ThunderXT83,
- ThunderXT88,
- ThunderX3T110,
- TSV110
+ #define ARM_PROCESSOR_FAMILY(ENUM) ENUM,
+ #include "llvm/TargetParser/AArch64TargetParserDef.inc"
+ #undef ARM_PROCESSOR_FAMILY
};
protected:
diff --git a/llvm/lib/TargetParser/CMakeLists.txt b/llvm/lib/TargetParser/CMakeLists.txt
index 742c87c20505f5..00f01a127ab316 100644
--- a/llvm/lib/TargetParser/CMakeLists.txt
+++ b/llvm/lib/TargetParser/CMakeLists.txt
@@ -38,5 +38,6 @@ add_llvm_component_library(LLVMTargetParser
DEPENDS
ARMTargetParserTableGen
+ AArch64TargetParserTableGen
RISCVTargetParserTableGen
)
diff --git a/llvm/utils/TableGen/CMakeLists.txt b/llvm/utils/TableGen/CMakeLists.txt
index 7b54a9059b680e..5285232e587a81 100644
--- a/llvm/utils/TableGen/CMakeLists.txt
+++ b/llvm/utils/TableGen/CMakeLists.txt
@@ -13,6 +13,7 @@ set(LLVM_LINK_COMPONENTS Support)
# ValueType definitions.
add_tablegen(llvm-min-tblgen LLVM_HEADERS
TableGen.cpp
+ ARMTargetDefEmitter.cpp
Attributes.cpp
DirectiveEmitter.cpp
IntrinsicEmitter.cpp
@@ -32,7 +33,6 @@ set(LLVM_LINK_COMPONENTS
add_tablegen(llvm-tblgen LLVM
DESTINATION "${LLVM_TOOLS_INSTALL_DIR}"
EXPORT LLVM
- ARMTargetDefEmitter.cpp
AsmMatcherEmitter.cpp
AsmWriterEmitter.cpp
Attributes.cpp
>From 50ce58ac47a8741d6ca99bf9b0b61ad01dab2828 Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Thu, 11 Apr 2024 11:47:37 +0100
Subject: [PATCH 3/5] clang-format
---
llvm/lib/Target/AArch64/AArch64Subtarget.h | 6 +++---
llvm/lib/Target/ARM/ARMSubtarget.h | 12 ++++++------
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 8ff5f9076f53b9..9cf1bed83d840d 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -39,9 +39,9 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
public:
enum ARMProcFamilyEnum : uint8_t {
Others,
- #define ARM_PROCESSOR_FAMILY(ENUM) ENUM,
- #include "llvm/TargetParser/AArch64TargetParserDef.inc"
- #undef ARM_PROCESSOR_FAMILY
+#define ARM_PROCESSOR_FAMILY(ENUM) ENUM,
+#include "llvm/TargetParser/AArch64TargetParserDef.inc"
+#undef ARM_PROCESSOR_FAMILY
};
protected:
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 3c07c91b9baad0..00239ff94b7ba5 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -49,9 +49,9 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
protected:
enum ARMProcFamilyEnum {
Others,
- #define ARM_PROCESSOR_FAMILY(ENUM) ENUM,
- #include "llvm/TargetParser/ARMTargetParserDef.inc"
- #undef ARM_PROCESSOR_FAMILY
+#define ARM_PROCESSOR_FAMILY(ENUM) ENUM,
+#include "llvm/TargetParser/ARMTargetParserDef.inc"
+#undef ARM_PROCESSOR_FAMILY
};
enum ARMProcClassEnum {
None,
@@ -61,9 +61,9 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
RClass
};
enum ARMArchEnum {
- #define ARM_ARCHITECTURE(ENUM) ENUM,
- #include "llvm/TargetParser/ARMTargetParserDef.inc"
- #undef ARM_ARCHITECTURE
+#define ARM_ARCHITECTURE(ENUM) ENUM,
+#include "llvm/TargetParser/ARMTargetParserDef.inc"
+#undef ARM_ARCHITECTURE
};
public:
>From 6e320b4d3aa4c28f894e735ba38448ee3b093ce2 Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Thu, 11 Apr 2024 12:33:45 +0100
Subject: [PATCH 4/5] Remove some non-existent ARMProcFamily values:
ARM: CortexM52, NeoverseN1, NeoverseN2, CortexR4F
AArch64: CortexX1C (still present in Target/ARM)
Since these have no corresponding Processor SubtargetFeature,
ARMProcFamily can never be set to these enum values.
---
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 1 -
llvm/lib/Target/ARM/ARMSubtarget.cpp | 3 ---
2 files changed, 4 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index bb268b2ba926cb..2609919a9596d9 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -144,7 +144,6 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
case CortexA78C:
case CortexR82:
case CortexX1:
- case CortexX1C:
PrefFunctionAlignment = Align(16);
PrefLoopAlignment = Align(32);
MaxBytesForLoopAlignment = 16;
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 20543f63e496f1..5e13d8fabe0485 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -298,7 +298,6 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
case CortexM3:
case CortexM7:
case CortexR52:
- case CortexM52:
case CortexX1:
case CortexX1C:
break;
@@ -313,8 +312,6 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
case Krait:
PreISelOperandLatencyAdjustment = 1;
break;
- case NeoverseN1:
- case NeoverseN2:
case NeoverseV1:
break;
case Swift:
>From 835a5edb7caa2b0d521295ce90d55565244af0f5 Mon Sep 17 00:00:00 2001
From: Tomas Matheson <tomas.matheson at arm.com>
Date: Tue, 23 Apr 2024 16:01:26 +0100
Subject: [PATCH 5/5] Address review comments
---
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 16 ++++++----------
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index 5253d7225d5183..db87ac3336c184 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -8,7 +8,7 @@
//
// This tablegen backend exports information about CPUs, FPUs, architectures,
// and features into a common format that can be used by both TargetParser and
-// the ARM backend.
+// the ARM and AArch64 backends.
//
//===----------------------------------------------------------------------===//
@@ -44,24 +44,20 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
<< "#endif\n\n";
const StringSet<> ARMProcFamilyVals =
gatherSubtargetFeatureFieldValues("ARMProcFamily");
- for (const StringRef &Family : ARMProcFamilyVals.keys()) {
+ for (const StringRef &Family : ARMProcFamilyVals.keys())
OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n";
- }
- OS << "\n#undef ARM_PROCESSOR_FAMILY\n";
- OS << "\n";
+ OS << "\n#undef ARM_PROCESSOR_FAMILY\n\n";
OS << "#ifndef ARM_ARCHITECTURE\n"
<< "#define ARM_ARCHITECTURE(ENUM)\n"
<< "#endif\n\n";
// This should correspond to instances of the Architecture tablegen class.
const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch");
- for (const StringRef &Arch : ARMArchVals.keys()) {
+ for (const StringRef &Arch : ARMArchVals.keys())
OS << "ARM_ARCHITECTURE(" << Arch << ")\n";
- }
- OS << "\n#undef ARM_ARCHITECTURE\n";
- OS << "\n";
+ OS << "\n#undef ARM_ARCHITECTURE\n\n";
}
static TableGen::Emitter::Opt
X("gen-arm-target-def", EmitARMTargetDef,
- "Generate the ARM Architecture information header.");
+ "Generate the ARM or AArch64 Architecture information header.");
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