[llvm] [RISCV] Add Sched classes for vector crypto instructions (PR #90068)

[Michael Maitland via llvm-commits]

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@@ -0,0 +1,208 @@
+//===- RISCVScheduleB.td - RISC-V Scheduling Definitions B -*- tablegen -*-===//
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michaelmaitland wrote:

updated

https://github.com/llvm/llvm-project/pull/90068