[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Momchil Velikov via llvm-commits]

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@@ -3095,12 +3095,10 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
     }
 
     if (RPI.isPaired() && RPI.isScalable()) {
-      unsigned PairRegs = AArch64::Z0_Z1 + (RPI.Reg1 - AArch64::Z0);
-      unsigned PnReg;
+      AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
+      unsigned PnReg = AFI->getPredicateRegForFillSpill();
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momchil-velikov wrote:

This looks good, the following are more like style remarks:
  * `PnReg` can be declared outside the loop. The you can initialise it under `if (!PtrueCreated) ...`, which seems more logical place to do it.
  * `PairRegs` has only one use and it's on the following line, you don't save anything by naming the corresponding expression

https://github.com/llvm/llvm-project/pull/77665