[llvm] Pre-commit lit test (PR #88858)
Abhinav Garg via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 24 05:57:41 PDT 2024
https://github.com/abhigargrepo updated https://github.com/llvm/llvm-project/pull/88858
>From e5545e88e4c2c4454b64f78f4c4bcfef8a9338c4 Mon Sep 17 00:00:00 2001
From: Abhinav <abhinav.garg at amd.com>
Date: Tue, 16 Apr 2024 11:42:11 +0530
Subject: [PATCH 1/3] Pre-commit lit test
This test will check the mode register in case of
constrained floating point operations.
---
.../AMDGPU/mode-register-fpconstrain.mir | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.mir
diff --git a/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.mir b/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.mir
new file mode 100644
index 00000000000000..fe4912c2e84cf6
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.mir
@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=si-mode-register -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+
+# The si-mode-register pass is changing the default mode for FP constrained operations.
+# It must ignore strictfp functions.
+
+--- |
+ define void @ignoreStrictFpFns() #0 {
+ ret void
+ }
+
+ attributes #0 = { strictfp }
+
+...
+---
+name: ignoreStrictFpFns
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+ ; GCN-LABEL: name: ignoreStrictFpFns
+ ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: S_WAITCNT 0
+ ; GCN-NEXT: S_SETREG_IMM32_B32_mode 1, 2177, implicit-def dead $mode, implicit $mode
+ ; GCN-NEXT: S_SETREG_IMM32_B32 0, 129, implicit-def $mode, implicit $mode
+ ; GCN-NEXT: renamable $vgpr0_vgpr1 = nofpexcept V_ADD_F64_e64 0, killed $vgpr0_vgpr1, 0, killed $vgpr2_vgpr3, 0, 0, implicit $mode, implicit $exec
+ ; GCN-NEXT: S_SETREG_IMM32_B32_mode 0, 2177, implicit-def dead $mode, implicit $mode
+ ; GCN-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit killed $vgpr0, implicit killed $vgpr1
+ S_WAITCNT 0
+ S_SETREG_IMM32_B32_mode 1, 2177, implicit-def dead $mode, implicit $mode
+ renamable $vgpr0_vgpr1 = nofpexcept V_ADD_F64_e64 0, killed $vgpr0_vgpr1, 0, killed $vgpr2_vgpr3, 0, 0, implicit $mode, implicit $exec
+ S_SETREG_IMM32_B32_mode 0, 2177, implicit-def dead $mode, implicit $mode
+ S_SETPC_B64_return undef $sgpr30_sgpr31, implicit killed $vgpr0, implicit killed $vgpr1
+
+...
>From 8deec78e724e36877fe794b20761d837f780ac97 Mon Sep 17 00:00:00 2001
From: Abhinav <abhinav.garg at amd.com>
Date: Fri, 19 Apr 2024 14:59:25 +0530
Subject: [PATCH 2/3] Pre-commit test to verify mode change in fp constrained
operations
This test will check the mode register change in case of constrained floating point operations.
---
.../AMDGPU/mode-register-fpconstrain.ll | 28 +++++++++++++++
.../AMDGPU/mode-register-fpconstrain.mir | 36 -------------------
2 files changed, 28 insertions(+), 36 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
delete mode 100644 llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.mir
diff --git a/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll b/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
new file mode 100644
index 00000000000000..fb80dd0d56983e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+
+; The si-mode-register pass is changing the default mode for FP constrained operations.
+; It must ignore for strictfp functions.
+
+define hidden fastcc double @ignoreStrictfp(double noundef %0, double noundef %1) unnamed_addr #0 {
+; GCN-LABEL: ignoreStrictfp:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 1
+; GCN-NEXT: s_nop 1
+; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0
+; GCN-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ tail call void @llvm.amdgcn.s.setreg(i32 2177, i32 1)
+ %3 = tail call double @llvm.experimental.constrained.fadd.f64(double %0, double %1, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
+ tail call void @llvm.amdgcn.s.setreg(i32 2177, i32 0)
+ ret double %3
+}
+
+declare void @llvm.amdgcn.s.setreg(i32 immarg, i32)
+
+declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
+
+attributes #0 = { strictfp }
diff --git a/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.mir b/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.mir
deleted file mode 100644
index fe4912c2e84cf6..00000000000000
--- a/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.mir
+++ /dev/null
@@ -1,36 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=si-mode-register -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
-
-# The si-mode-register pass is changing the default mode for FP constrained operations.
-# It must ignore strictfp functions.
-
---- |
- define void @ignoreStrictFpFns() #0 {
- ret void
- }
-
- attributes #0 = { strictfp }
-
-...
----
-name: ignoreStrictFpFns
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
- ; GCN-LABEL: name: ignoreStrictFpFns
- ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: S_WAITCNT 0
- ; GCN-NEXT: S_SETREG_IMM32_B32_mode 1, 2177, implicit-def dead $mode, implicit $mode
- ; GCN-NEXT: S_SETREG_IMM32_B32 0, 129, implicit-def $mode, implicit $mode
- ; GCN-NEXT: renamable $vgpr0_vgpr1 = nofpexcept V_ADD_F64_e64 0, killed $vgpr0_vgpr1, 0, killed $vgpr2_vgpr3, 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: S_SETREG_IMM32_B32_mode 0, 2177, implicit-def dead $mode, implicit $mode
- ; GCN-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31, implicit killed $vgpr0, implicit killed $vgpr1
- S_WAITCNT 0
- S_SETREG_IMM32_B32_mode 1, 2177, implicit-def dead $mode, implicit $mode
- renamable $vgpr0_vgpr1 = nofpexcept V_ADD_F64_e64 0, killed $vgpr0_vgpr1, 0, killed $vgpr2_vgpr3, 0, 0, implicit $mode, implicit $exec
- S_SETREG_IMM32_B32_mode 0, 2177, implicit-def dead $mode, implicit $mode
- S_SETPC_B64_return undef $sgpr30_sgpr31, implicit killed $vgpr0, implicit killed $vgpr1
-
-...
>From 905389dfdd854a33a9fdbb5db25e3a41f0c84e7e Mon Sep 17 00:00:00 2001
From: Abhinav <abhinav.garg at amd.com>
Date: Wed, 24 Apr 2024 18:25:13 +0530
Subject: [PATCH 3/3] Pre-commit test to verify mode change in fp constrained
operations
This test will check the mode register change in case of constrained floating point operations.
---
.../AMDGPU/mode-register-fpconstrain.ll | 29 ++++++++++++++-----
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll b/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
index fb80dd0d56983e..3a8dd19225d799 100644
--- a/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
+++ b/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
@@ -4,25 +4,40 @@
; The si-mode-register pass is changing the default mode for FP constrained operations.
; It must ignore for strictfp functions.
-define hidden fastcc double @ignoreStrictfp(double noundef %0, double noundef %1) unnamed_addr #0 {
+define double @ignoreStrictfp(double noundef %a, double noundef %b) #0 {
; GCN-LABEL: ignoreStrictfp:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 1
; GCN-NEXT: s_nop 1
-; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0
+; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0
; GCN-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
; GCN-NEXT: s_setpc_b64 s[30:31]
tail call void @llvm.amdgcn.s.setreg(i32 2177, i32 1)
- %3 = tail call double @llvm.experimental.constrained.fadd.f64(double %0, double %1, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
- tail call void @llvm.amdgcn.s.setreg(i32 2177, i32 0)
- ret double %3
+ %val = tail call double @llvm.experimental.constrained.fadd.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
+ ret double %val
+}
+
+define double @set_fpenv(double noundef %a, double noundef %b) #0 {
+; GCN-LABEL: set_fpenv:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 23), 4
+; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 0, 5), 0
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0
+; GCN-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
+; GCN-NEXT: s_setpc_b64 s[30:31]
+entry:
+ call void @llvm.set.fpenv.i64(i64 4)
+ %val = tail call double @llvm.experimental.constrained.fadd.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
+ ret double %val
}
declare void @llvm.amdgcn.s.setreg(i32 immarg, i32)
declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
+declare void @llvm.set.fpenv.i64(i64)
+
attributes #0 = { strictfp }
More information about the llvm-commits
mailing list