[llvm] [NFC][RISCV] Keep AVLReg define instr inside VSETVLInfo (PR #89180)
Piyou Chen via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 24 07:33:40 PDT 2024
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/89180
>From b712c806f7e2eaf4c81ebdf1c82021edb0ca53fa Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 18 Apr 2024 00:30:46 -0700
Subject: [PATCH 1/2] [RISCV] Keep AVLReg define instr inside VSETVLInfo
Currently, the vsetvli pass track the define instruction through MRI->getVRegDef due to the SSA form.
This patch keeps the AVLReg DefMI within VSETVLInfo during construction. And replace MRI->getVRegDef(AVLReg) with getAVLRegDefMI().
This information is useful when vsetvli pass live in post-ra situation.
The testcases don't change because the VReg always has a unique def in SSA.
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 56 ++++++++++++--------
1 file changed, 35 insertions(+), 21 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index a57d6afcb25586..f68310f7815f85 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -156,7 +156,7 @@ static std::optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
}
}
-static bool isNonZeroLoadImmediate(MachineInstr &MI) {
+static bool isNonZeroLoadImmediate(const MachineInstr &MI) {
return MI.getOpcode() == RISCV::ADDI &&
MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
MI.getOperand(1).getReg() == RISCV::X0 &&
@@ -448,6 +448,8 @@ class VSETVLIInfo {
unsigned AVLImm;
};
+ const MachineInstr *AVLDefMI;
+
enum : uint8_t {
Uninitialized,
AVLIsReg,
@@ -464,7 +466,7 @@ class VSETVLIInfo {
public:
VSETVLIInfo()
- : AVLImm(0), TailAgnostic(false), MaskAgnostic(false),
+ : AVLImm(0), AVLDefMI(nullptr), TailAgnostic(false), MaskAgnostic(false),
SEWLMULRatioOnly(false) {}
static VSETVLIInfo getUnknown() {
@@ -488,6 +490,8 @@ class VSETVLIInfo {
State = AVLIsImm;
}
+ void setAVLDefMI(const MachineInstr *DefMI) { AVLDefMI = DefMI; }
+
bool hasAVLImm() const { return State == AVLIsImm; }
bool hasAVLReg() const { return State == AVLIsReg; }
Register getAVLReg() const {
@@ -499,13 +503,16 @@ class VSETVLIInfo {
return AVLImm;
}
+ const MachineInstr *getAVLDefMI() const { return AVLDefMI; }
+
void setAVL(VSETVLIInfo Info) {
assert(Info.isValid());
if (Info.isUnknown())
setUnknown();
- else if (Info.hasAVLReg())
+ else if (Info.hasAVLReg()) {
setAVLReg(Info.getAVLReg());
- else {
+ setAVLDefMI(Info.getAVLDefMI());
+ } else {
assert(Info.hasAVLImm());
setAVLImm(Info.getAVLImm());
}
@@ -522,8 +529,7 @@ class VSETVLIInfo {
if (hasAVLReg()) {
if (getAVLReg() == RISCV::X0)
return true;
- if (MachineInstr *MI = MRI.getVRegDef(getAVLReg());
- MI && isNonZeroLoadImmediate(*MI))
+ if (getAVLDefMI() && isNonZeroLoadImmediate(*getAVLDefMI()))
return true;
return false;
}
@@ -836,7 +842,8 @@ INITIALIZE_PASS(RISCVCoalesceVSETVLI, "riscv-coalesce-vsetvli",
// Return a VSETVLIInfo representing the changes made by this VSETVLI or
// VSETIVLI instruction.
-static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
+static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI,
+ const MachineRegisterInfo &MRI) {
VSETVLIInfo NewInfo;
if (MI.getOpcode() == RISCV::PseudoVSETIVLI) {
NewInfo.setAVLImm(MI.getOperand(1).getImm());
@@ -847,6 +854,8 @@ static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
assert((AVLReg != RISCV::X0 || MI.getOperand(0).getReg() != RISCV::X0) &&
"Can't handle X0, X0 vsetvli yet");
NewInfo.setAVLReg(AVLReg);
+ if (AVLReg.isVirtual())
+ NewInfo.setAVLDefMI(MRI.getVRegDef(AVLReg));
}
NewInfo.setVTYPE(MI.getOperand(2).getImm());
@@ -919,6 +928,8 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
InstrInfo.setAVLImm(Imm);
} else {
InstrInfo.setAVLReg(VLOp.getReg());
+ if (VLOp.getReg().isVirtual())
+ InstrInfo.setAVLDefMI(MRI->getVRegDef(VLOp.getReg()));
}
} else {
assert(isScalarExtractInstr(MI));
@@ -936,9 +947,10 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
// register AVLs to avoid extending live ranges without being sure we can
// kill the original source reg entirely.
if (InstrInfo.hasAVLReg() && InstrInfo.getAVLReg().isVirtual()) {
- MachineInstr *DefMI = MRI->getVRegDef(InstrInfo.getAVLReg());
- if (DefMI && isVectorConfigInstr(*DefMI)) {
- VSETVLIInfo DefInstrInfo = getInfoForVSETVLI(*DefMI);
+ if (InstrInfo.getAVLDefMI() &&
+ isVectorConfigInstr(*InstrInfo.getAVLDefMI())) {
+ VSETVLIInfo DefInstrInfo =
+ getInfoForVSETVLI(*InstrInfo.getAVLDefMI(), *MRI);
if (DefInstrInfo.hasSameVLMAX(InstrInfo) &&
(DefInstrInfo.hasAVLImm() || DefInstrInfo.getAVLReg() == RISCV::X0)) {
InstrInfo.setAVL(DefInstrInfo);
@@ -978,9 +990,9 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
// same, we can use the X0, X0 form.
if (Info.hasSameVLMAX(PrevInfo) && Info.hasAVLReg() &&
Info.getAVLReg().isVirtual()) {
- if (MachineInstr *DefMI = MRI->getVRegDef(Info.getAVLReg())) {
- if (isVectorConfigInstr(*DefMI)) {
- VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
+ if (Info.getAVLDefMI()) {
+ if (isVectorConfigInstr(*Info.getAVLDefMI())) {
+ VSETVLIInfo DefInfo = getInfoForVSETVLI(*Info.getAVLDefMI(), *MRI);
if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) {
BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
@@ -1100,9 +1112,9 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
// VSETVLI here.
if (Require.hasAVLReg() && Require.getAVLReg().isVirtual() &&
CurInfo.hasCompatibleVTYPE(Used, Require)) {
- if (MachineInstr *DefMI = MRI->getVRegDef(Require.getAVLReg())) {
- if (isVectorConfigInstr(*DefMI)) {
- VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
+ if (Require.getAVLDefMI()) {
+ if (isVectorConfigInstr(*Require.getAVLDefMI())) {
+ VSETVLIInfo DefInfo = getInfoForVSETVLI(*Require.getAVLDefMI(), *MRI);
if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVLMAX(CurInfo))
return false;
}
@@ -1189,13 +1201,15 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
const MachineInstr &MI) const {
if (isVectorConfigInstr(MI)) {
- Info = getInfoForVSETVLI(MI);
+ Info = getInfoForVSETVLI(MI, *MRI);
return;
}
if (RISCV::isFaultFirstLoad(MI)) {
// Update AVL to vl-output of the fault first load.
Info.setAVLReg(MI.getOperand(1).getReg());
+ if (MI.getOperand(1).getReg().isVirtual())
+ Info.setAVLDefMI(MRI->getVRegDef(MI.getOperand(1).getReg()));
return;
}
@@ -1315,7 +1329,7 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
// We found a VSET(I)VLI make sure it matches the output of the
// predecessor block.
- VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
+ VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI, *MRI);
if (!DefInfo.hasSameAVL(PBBInfo.Exit) ||
!DefInfo.hasSameVTYPE(PBBInfo.Exit))
return true;
@@ -1464,7 +1478,7 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
// we need to prove the value is available at the point we're going
// to insert the vsetvli at.
if (AvailableInfo.hasAVLReg() && RISCV::X0 != AvailableInfo.getAVLReg()) {
- MachineInstr *AVLDefMI = MRI->getVRegDef(AvailableInfo.getAVLReg());
+ const MachineInstr *AVLDefMI = AvailableInfo.getAVLDefMI();
if (!AVLDefMI)
return;
// This is an inline dominance check which covers the case of
@@ -1550,8 +1564,8 @@ static bool canMutatePriorConfig(const MachineInstr &PrevMI,
if (Used.VLZeroness) {
if (isVLPreservingConfig(PrevMI))
return false;
- if (!getInfoForVSETVLI(PrevMI).hasEquallyZeroAVL(getInfoForVSETVLI(MI),
- MRI))
+ if (!getInfoForVSETVLI(PrevMI, MRI)
+ .hasEquallyZeroAVL(getInfoForVSETVLI(MI, MRI), MRI))
return false;
}
>From cae0c6332cfabdd74f8ec600e60eab2cd37537fa Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 24 Apr 2024 07:24:12 -0700
Subject: [PATCH 2/2] Get rid of MRI from hasNonZeroAVL and hasEquallyZeroAVL
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index f68310f7815f85..af743d41fd86f5 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -523,7 +523,7 @@ class VSETVLIInfo {
bool getTailAgnostic() const { return TailAgnostic; }
bool getMaskAgnostic() const { return MaskAgnostic; }
- bool hasNonZeroAVL(const MachineRegisterInfo &MRI) const {
+ bool hasNonZeroAVL() const {
if (hasAVLImm())
return getAVLImm() > 0;
if (hasAVLReg()) {
@@ -536,11 +536,10 @@ class VSETVLIInfo {
return false;
}
- bool hasEquallyZeroAVL(const VSETVLIInfo &Other,
- const MachineRegisterInfo &MRI) const {
+ bool hasEquallyZeroAVL(const VSETVLIInfo &Other) const {
if (hasSameAVL(Other))
return true;
- return (hasNonZeroAVL(MRI) && Other.hasNonZeroAVL(MRI));
+ return (hasNonZeroAVL() && Other.hasNonZeroAVL());
}
bool hasSameAVL(const VSETVLIInfo &Other) const {
@@ -635,7 +634,7 @@ class VSETVLIInfo {
if (Used.VLAny && !(hasSameAVL(Require) && hasSameVLMAX(Require)))
return false;
- if (Used.VLZeroness && !hasEquallyZeroAVL(Require, MRI))
+ if (Used.VLZeroness && !hasEquallyZeroAVL(Require))
return false;
return hasCompatibleVTYPE(Used, Require);
@@ -1170,7 +1169,7 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
// variant, so we avoid the transform to prevent extending live range of an
// avl register operand.
// TODO: We can probably relax this for immediates.
- bool EquallyZero = IncomingInfo.hasEquallyZeroAVL(PrevInfo, *MRI) &&
+ bool EquallyZero = IncomingInfo.hasEquallyZeroAVL(PrevInfo) &&
IncomingInfo.hasSameVLMAX(PrevInfo);
if (Demanded.VLAny || (Demanded.VLZeroness && !EquallyZero))
Info.setAVL(IncomingInfo);
@@ -1565,7 +1564,7 @@ static bool canMutatePriorConfig(const MachineInstr &PrevMI,
if (isVLPreservingConfig(PrevMI))
return false;
if (!getInfoForVSETVLI(PrevMI, MRI)
- .hasEquallyZeroAVL(getInfoForVSETVLI(MI, MRI), MRI))
+ .hasEquallyZeroAVL(getInfoForVSETVLI(MI, MRI)))
return false;
}
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