[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Momchil Velikov via llvm-commits]

momchil-velikov wrote:

> I guess my point more widely was that when choosing a different calling convention (other than the one we currently implement), the choice of PN8 may not be right.

All right, how about this strategy:
* don't optimise for hypothetical calling conventions
* in `determineCalleeSaves`, make sure we chose an already saved register, or, if there are none, choose `pn8` if the calling convention of the function is one where we know `pn8` is a callee saved register:
  * `AArch64_SVE_VectorCall`
  *  `AArch64_SME_ABI_Support_Routines_PreserveMost_From_X0`
  * `AArch64_SME_ABI_Support_Routines_PreserveMost_From_X2`
 
  Not a correctness issue if we miss some.
* everywhere else we use only `AFI->getPredicateRegForFillSpill() != 0` as the condition determining we can and should load/store in pairs



https://github.com/llvm/llvm-project/pull/77665