[llvm] [AArch64][CodeGen] Add patterns for small negative VScale const (PR #89607)

[via llvm-commits]

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@@ -2583,6 +2583,27 @@ let Predicates = [HasSVEorSME] in {
                                sub_32)>;
   }
 
+  // Add NoUseScalarIncVL to avoid affecting for patterns with UseScalarIncVL
+  let Predicates = [NoUseScalarIncVL] in {
+    def : Pat<(add GPR64:$op, (vscale (sve_rdvl_imm i32:$imm))),
+              (ADDXrs GPR64:$op, (RDVLI_XI $imm), 0)>;
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vfdff wrote:

Yes, delete the pattern `(vscale (sve_rdvl_imm i32:$imm)`, thanks
I think `cnth   x8, all, mul #2` will need an extra `mull unit` before, but it indeed doesn't after checking with with colleagues

https://github.com/llvm/llvm-project/pull/89607