[llvm] 80f510b - [RISCV] Use lookup tables to find CVTFOpc
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 24 09:29:34 PDT 2024
Author: Michael Maitland
Date: 2024-04-24T09:29:21-07:00
New Revision: 80f510bbc9561324fc13bac22aad2e3ef47a59c5
URL: https://github.com/llvm/llvm-project/commit/80f510bbc9561324fc13bac22aad2e3ef47a59c5
DIFF: https://github.com/llvm/llvm-project/commit/80f510bbc9561324fc13bac22aad2e3ef47a59c5.diff
LOG: [RISCV] Use lookup tables to find CVTFOpc
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 353fb3291aef48..6529ab7a84a133 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17787,6 +17787,18 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
return TailMBB;
}
+// Helper to find Masked Pseudo instruction from MC instruction, LMUL and SEW.
+static const RISCV::RISCVMaskedPseudoInfo *
+lookupMaskedIntrinsic(uint16_t MCOpcode, RISCVII::VLMUL LMul, unsigned SEW) {
+ const RISCVVInversePseudosTable::PseudoInfo *Inverse =
+ RISCVVInversePseudosTable::getBaseInfo(MCOpcode, LMul, SEW);
+ assert(Inverse && "Unexpected LMUL and SEW pair for instruction");
+ const RISCV::RISCVMaskedPseudoInfo *Masked =
+ RISCV::lookupMaskedIntrinsicByUnmasked(Inverse->Pseudo);
+ assert(Masked && "Could not find masked instruction for LMUL and SEW pair");
+ return Masked;
+}
+
static MachineBasicBlock *emitVFROUND_NOEXCEPT_MASK(MachineInstr &MI,
MachineBasicBlock *BB,
unsigned CVTXOpc) {
@@ -17824,80 +17836,9 @@ static MachineBasicBlock *emitVFROUND_NOEXCEPT_MASK(MachineInstr &MI,
unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm();
// There is no E8 variant for VFCVT_F_X.
assert(Log2SEW >= 4);
- // Since MI (VFROUND) isn't SEW specific, we cannot use a macro to make
- // handling of
diff erent (LMUL, SEW) pairs easier because we need to pull the
- // SEW immediate from MI, and that information is not avaliable during macro
- // expansion.
- unsigned CVTFOpc;
- if (Log2SEW == 4) {
- switch (LMul) {
- case RISCVII::LMUL_1:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M1_E16_MASK;
- break;
- case RISCVII::LMUL_2:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M2_E16_MASK;
- break;
- case RISCVII::LMUL_4:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M4_E16_MASK;
- break;
- case RISCVII::LMUL_8:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M8_E16_MASK;
- break;
- case RISCVII::LMUL_F2:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_MF2_E16_MASK;
- break;
- case RISCVII::LMUL_F4:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_MF4_E16_MASK;
- break;
- case RISCVII::LMUL_F8:
- case RISCVII::LMUL_RESERVED:
- llvm_unreachable("Unexpected LMUL and SEW combination value for MI.");
- }
- } else if (Log2SEW == 5) {
- switch (LMul) {
- case RISCVII::LMUL_1:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M1_E32_MASK;
- break;
- case RISCVII::LMUL_2:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M2_E32_MASK;
- break;
- case RISCVII::LMUL_4:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M4_E32_MASK;
- break;
- case RISCVII::LMUL_8:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M8_E32_MASK;
- break;
- case RISCVII::LMUL_F2:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_MF2_E32_MASK;
- break;
- case RISCVII::LMUL_F4:
- case RISCVII::LMUL_F8:
- case RISCVII::LMUL_RESERVED:
- llvm_unreachable("Unexpected LMUL and SEW combination value for MI.");
- }
- } else if (Log2SEW == 6) {
- switch (LMul) {
- case RISCVII::LMUL_1:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M1_E64_MASK;
- break;
- case RISCVII::LMUL_2:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M2_E64_MASK;
- break;
- case RISCVII::LMUL_4:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M4_E64_MASK;
- break;
- case RISCVII::LMUL_8:
- CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M8_E64_MASK;
- break;
- case RISCVII::LMUL_F2:
- case RISCVII::LMUL_F4:
- case RISCVII::LMUL_F8:
- case RISCVII::LMUL_RESERVED:
- llvm_unreachable("Unexpected LMUL and SEW combination value for MI.");
- }
- } else {
- llvm_unreachable("Unexpected LMUL and SEW combination value for MI.");
- }
+ unsigned CVTFOpc =
+ lookupMaskedIntrinsic(RISCV::VFCVT_F_X_V, LMul, 1 << Log2SEW)
+ ->MaskedPseudo;
BuildMI(*BB, MI, DL, TII.get(CVTFOpc))
.add(MI.getOperand(0))
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 435cd7f84c6122..e9715b40adc079 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -3593,7 +3593,7 @@ multiclass VPseudoConversion<VReg RetClass,
int sew = 0,
int TargetConstraintType = 1> {
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
- let VLMul = MInfo.value in {
+ let VLMul = MInfo.value, SEW=sew in {
def suffix : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint, TargetConstraintType>;
def suffix # "_MASK" : VPseudoUnaryMask<RetClass, Op1Class,
Constraint, TargetConstraintType>,
@@ -3607,7 +3607,7 @@ multiclass VPseudoConversionRoundingMode<VReg RetClass,
string Constraint = "",
int sew = 0,
int TargetConstraintType = 1> {
- let VLMul = MInfo.value in {
+ let VLMul = MInfo.value, SEW=sew in {
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
def suffix : VPseudoUnaryNoMaskRoundingMode<RetClass, Op1Class, Constraint, TargetConstraintType>;
def suffix # "_MASK" : VPseudoUnaryMaskRoundingMode<RetClass, Op1Class,
@@ -3624,7 +3624,7 @@ multiclass VPseudoConversionRM<VReg RetClass,
string Constraint = "",
int sew = 0,
int TargetConstraintType = 1> {
- let VLMul = MInfo.value in {
+ let VLMul = MInfo.value, SEW=sew in {
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
def suffix : VPseudoUnaryNoMask_FRM<RetClass, Op1Class,
Constraint, TargetConstraintType>;
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