[llvm] [AArch64][CodeGen] Add patterns for small negative VScale const (PR #89607)

[Paul Walker via llvm-commits]

================
@@ -2583,6 +2583,27 @@ let Predicates = [HasSVEorSME] in {
                                sub_32)>;
   }
 
+  // Add NoUseScalarIncVL to avoid affecting for patterns with UseScalarIncVL
+  let Predicates = [NoUseScalarIncVL] in {
+    def : Pat<(add GPR64:$op, (vscale (sve_rdvl_imm i32:$imm))),
+              (ADDXrs GPR64:$op, (RDVLI_XI $imm), 0)>;
----------------
paulwalker-arm wrote:

Is this necessary?  We already have patterns for `(vscale (sve_rdvl_imm i32:$imm)` that will emit `(RDVLI_XI $imm)` so I don't think it hits the negated case this patch fixes.

https://github.com/llvm/llvm-project/pull/89607