[llvm] [AMDGPU] Fix mode register pass for constrained FP operations (PR #90085)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff b77416ea156acdec766c59d4781e6086963a26a7 3f5392de2d4322f5a6d2fc973c218f59fadb34c6 -- llvm/lib/Target/AMDGPU/SIModeRegister.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIModeRegister.cpp b/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
index 44d72f02d0..295c2068a8 100644
--- a/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
+++ b/llvm/lib/Target/AMDGPU/SIModeRegister.cpp
@@ -430,7 +430,7 @@ void SIModeRegister::processBlockPhase3(MachineBasicBlock &MBB,
 }
 
 bool SIModeRegister::runOnMachineFunction(MachineFunction &MF) {
-  // This pass should not modify the rounding mode in case 
+  // This pass should not modify the rounding mode in case
   // of constrained FP operations with dynamic rounding modes.
   // As per llvm lang ref, functions with such constrained
   // operations must have strictfp attribute.

``````````

</details>


https://github.com/llvm/llvm-project/pull/90085