[llvm] [AArch64][GlobalISel] Select G_ICMP Zero Instruction (PR #90054)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 25 06:59:37 PDT 2024
https://github.com/chuongg3 created https://github.com/llvm/llvm-project/pull/90054
None
>From 455f4957dda94fea8c2f20b2f0241d1325691b5a Mon Sep 17 00:00:00 2001
From: Tuan Chuong Goh <chuong.goh at arm.com>
Date: Thu, 25 Apr 2024 08:55:08 +0000
Subject: [PATCH 1/2] [AArch64][GlobalISel] Pre-commit Tests for Select G_ICMP
Zero Instruction
---
llvm/test/CodeGen/AArch64/icmp.ll | 1114 +++++++++++++++++++++++++++++
1 file changed, 1114 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/icmp.ll b/llvm/test/CodeGen/AArch64/icmp.ll
index 8e10847e7aae34..de1a45204836cc 100644
--- a/llvm/test/CodeGen/AArch64/icmp.ll
+++ b/llvm/test/CodeGen/AArch64/icmp.ll
@@ -319,3 +319,1117 @@ entry:
%s = select <32 x i1> %c, <32 x i8> %d, <32 x i8> %e
ret <32 x i8> %s
}
+
+; ===== ICMP Zero RHS =====
+
+define <8 x i1> @icmp_eq_v8i8_Zero_RHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_eq_v8i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v8i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_eq_v16i8_Zero_RHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_eq_v16i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v16i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_eq_v4i16_Zero_RHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_eq_v4i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v4i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_eq_v8i16_Zero_RHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_eq_v8i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v8i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_eq_v2i32_Zero_RHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_eq_v2i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v2i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <2 x i32> %a, <i32 0, i32 0>
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_eq_v4i32_Zero_RHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_eq_v4i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v4i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_eq_v2i64_Zero_RHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_eq_v2i64_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v2i64_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <2 x i64> %a, <i64 0, i64 0>
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_sge_v8i8_Zero_RHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sge_v8i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v8i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_sge_v16i8_Zero_RHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sge_v16i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v16i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_sge_v4i16_Zero_RHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sge_v4i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v4i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4h, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_sge_v8i16_Zero_RHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sge_v8i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v8i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_sge_v2i32_Zero_RHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sge_v2i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v2i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <2 x i32> %a, <i32 0, i32 0>
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_sge_v4i32_Zero_RHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sge_v4i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v4i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_sge_v2i64_Zero_RHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_sge_v2i64_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v2i64_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <2 x i64> %a, <i64 0, i64 0>
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_sgt_v8i8_Zero_RHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v8i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v8i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_sgt_v16i8_Zero_RHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v16i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v16i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_sgt_v4i16_Zero_RHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v4i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v4i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4h, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_sgt_v8i16_Zero_RHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v8i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v8i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_sgt_v2i32_Zero_RHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v2i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v2i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <2 x i32> %a, <i32 0, i32 0>
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_sgt_v4i32_Zero_RHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v4i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v4i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_sgt_v2i64_Zero_RHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v2i64_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v2i64_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <2 x i64> %a, <i64 0, i64 0>
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_sle_v8i8_Zero_RHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sle_v8i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v8i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_sle_v16i8_Zero_RHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sle_v16i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v16i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_sle_v4i16_Zero_RHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sle_v4i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v4i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_sle_v8i16_Zero_RHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sle_v8i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v8i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_sle_v2i32_Zero_RHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sle_v2i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v2i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2s, v1.2s, v0.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <2 x i32> %a, <i32 0, i32 0>
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_sle_v4i32_Zero_RHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sle_v4i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v4i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_sle_v2i64_Zero_RHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_sle_v2i64_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v2i64_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <2 x i64> %a, <i64 0, i64 0>
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_slt_v8i8_Zero_RHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_slt_v8i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v8i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_slt_v16i8_Zero_RHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_slt_v16i8_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v16i8_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_slt_v4i16_Zero_RHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_slt_v4i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v4i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_slt_v8i16_Zero_RHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_slt_v8i16_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v8i16_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_slt_v2i32_Zero_RHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_slt_v2i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v2i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2s, v1.2s, v0.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <2 x i32> %a, <i32 0, i32 0>
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_slt_v4i32_Zero_RHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_slt_v4i32_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v4i32_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_slt_v2i64_Zero_RHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_slt_v2i64_Zero_RHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v2i64_Zero_RHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <2 x i64> %a, <i64 0, i64 0>
+ ret <2 x i1> %c
+}
+
+; ===== ICMP Zero LHS =====
+
+define <8 x i1> @icmp_eq_v8i8_Zero_LHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_eq_v8i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v8i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_eq_v16i8_Zero_LHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_eq_v16i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v16i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_eq_v4i16_Zero_LHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_eq_v4i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v4i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_eq_v8i16_Zero_LHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_eq_v8i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v8i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_eq_v2i32_Zero_LHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_eq_v2i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v2i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.2s, v1.2s, v0.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <2 x i32> <i32 0, i32 0>, %a
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_eq_v4i32_Zero_LHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_eq_v4i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v4i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_eq_v2i64_Zero_LHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_eq_v2i64_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_eq_v2i64_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmeq v0.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp eq <2 x i64> <i64 0, i64 0>, %a
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_sge_v8i8_Zero_LHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sge_v8i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v8i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_sge_v16i8_Zero_LHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sge_v16i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v16i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_sge_v4i16_Zero_LHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sge_v4i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v4i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_sge_v8i16_Zero_LHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sge_v8i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v8i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_sge_v2i32_Zero_LHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sge_v2i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v2i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2s, v1.2s, v0.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <2 x i32> <i32 0, i32 0>, %a
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_sge_v4i32_Zero_LHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sge_v4i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v4i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_sge_v2i64_Zero_LHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_sge_v2i64_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmle v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sge_v2i64_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp sge <2 x i64> <i64 0, i64 0>, %a
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_sgt_v8i8_Zero_LHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v8i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v8i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_sgt_v16i8_Zero_LHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v16i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v16i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_sgt_v4i16_Zero_LHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v4i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v4i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_sgt_v8i16_Zero_LHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v8i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v8i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_sgt_v2i32_Zero_LHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v2i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v2i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2s, v1.2s, v0.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <2 x i32> <i32 0, i32 0>, %a
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_sgt_v4i32_Zero_LHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v4i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v4i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_sgt_v2i64_Zero_LHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_sgt_v2i64_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmlt v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sgt_v2i64_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp sgt <2 x i64> <i64 0, i64 0>, %a
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_sle_v8i8_Zero_LHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sle_v8i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v8i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_sle_v16i8_Zero_LHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_sle_v16i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v16i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_sle_v4i16_Zero_LHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sle_v4i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v4i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4h, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_sle_v8i16_Zero_LHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_sle_v8i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v8i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_sle_v2i32_Zero_LHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sle_v2i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v2i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <2 x i32> <i32 0, i32 0>, %a
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_sle_v4i32_Zero_LHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_sle_v4i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v4i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_sle_v2i64_Zero_LHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_sle_v2i64_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmge v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_sle_v2i64_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmge v0.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp sle <2 x i64> <i64 0, i64 0>, %a
+ ret <2 x i1> %c
+}
+
+define <8 x i1> @icmp_slt_v8i8_Zero_LHS(<8 x i8> %a) {
+; CHECK-SD-LABEL: icmp_slt_v8i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.8b, v0.8b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v8i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <8 x i1> %c
+}
+
+define <16 x i1> @icmp_slt_v16i8_Zero_LHS(<16 x i8> %a) {
+; CHECK-SD-LABEL: icmp_slt_v16i8_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.16b, v0.16b, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v16i8_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
+ ret <16 x i1> %c
+}
+
+define <4 x i1> @icmp_slt_v4i16_Zero_LHS(<4 x i16> %a) {
+; CHECK-SD-LABEL: icmp_slt_v4i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.4h, v0.4h, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v4i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4h, v0.4h, v1.4h
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
+ ret <4 x i1> %c
+}
+
+define <8 x i1> @icmp_slt_v8i16_Zero_LHS(<8 x i16> %a) {
+; CHECK-SD-LABEL: icmp_slt_v8i16_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.8h, v0.8h, #0
+; CHECK-SD-NEXT: xtn v0.8b, v0.8h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v8i16_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
+ ret <8 x i1> %c
+}
+
+define <2 x i1> @icmp_slt_v2i32_Zero_LHS(<2 x i32> %a) {
+; CHECK-SD-LABEL: icmp_slt_v2i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.2s, v0.2s, #0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v2i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <2 x i32> <i32 0, i32 0>, %a
+ ret <2 x i1> %c
+}
+
+define <4 x i1> @icmp_slt_v4i32_Zero_LHS(<4 x i32> %a) {
+; CHECK-SD-LABEL: icmp_slt_v4i32_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v4i32_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
+ ret <4 x i1> %c
+}
+
+define <2 x i1> @icmp_slt_v2i64_Zero_LHS(<2 x i64> %a) {
+; CHECK-SD-LABEL: icmp_slt_v2i64_Zero_LHS:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmgt v0.2d, v0.2d, #0
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: icmp_slt_v2i64_Zero_LHS:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
+; CHECK-GI-NEXT: cmgt v0.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
+ %c = icmp slt <2 x i64> <i64 0, i64 0>, %a
+ ret <2 x i1> %c
+}
>From 257a3a835f7c39471b167ba7061c7cbc879f0c8a Mon Sep 17 00:00:00 2001
From: Tuan Chuong Goh <chuong.goh at arm.com>
Date: Thu, 25 Apr 2024 12:26:43 +0000
Subject: [PATCH 2/2] [AArch64][GlobalISel] Select G_ICMP Zero Instruction
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 46 +
llvm/test/CodeGen/AArch64/aarch64-addv.ll | 25 +-
llvm/test/CodeGen/AArch64/arm64-vabs.ll | 227 ++--
llvm/test/CodeGen/AArch64/icmp.ll | 1070 +++++------------
.../AArch64/neon-bitwise-instructions.ll | 37 +-
.../AArch64/neon-compare-instructions.ll | 490 +++-----
6 files changed, 624 insertions(+), 1271 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index a7abb58064a535..bf331b97069ba2 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -5397,6 +5397,52 @@ def : Pat<(AArch64bsp (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
def : Pat<(AArch64bsp (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
(BSPv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
+multiclass SelectSetCCZeroRHS<PatFrags InFrag, string INST> {
+ def : Pat<(v8i8 (InFrag (v8i8 V64:$Rn), immAllZerosV)),
+ (v8i8 (!cast<Instruction>(INST # v8i8rz) (v8i8 V64:$Rn)))>;
+ def : Pat<(v16i8 (InFrag (v16i8 V128:$Rn), immAllZerosV)),
+ (v16i8 (!cast<Instruction>(INST # v16i8rz) (v16i8 V128:$Rn)))>;
+ def : Pat<(v4i16 (InFrag (v4i16 V64:$Rn), immAllZerosV)),
+ (v4i16 (!cast<Instruction>(INST # v4i16rz) (v4i16 V64:$Rn)))>;
+ def : Pat<(v8i16 (InFrag (v8i16 V128:$Rn), immAllZerosV)),
+ (v8i16 (!cast<Instruction>(INST # v8i16rz) (v8i16 V128:$Rn)))>;
+ def : Pat<(v2i32 (InFrag (v2i32 V64:$Rn), immAllZerosV)),
+ (v2i32 (!cast<Instruction>(INST # v2i32rz) (v2i32 V64:$Rn)))>;
+ def : Pat<(v4i32 (InFrag (v4i32 V128:$Rn), immAllZerosV)),
+ (v4i32 (!cast<Instruction>(INST # v4i32rz) (v4i32 V128:$Rn)))>;
+ def : Pat<(v2i64 (InFrag (v2i64 V128:$Rn), immAllZerosV)),
+ (v2i64 (!cast<Instruction>(INST # v2i64rz) (v2i64 V128:$Rn)))>;
+}
+
+defm : SelectSetCCZeroRHS<seteq, "CMEQ">;
+defm : SelectSetCCZeroRHS<setgt, "CMGT">;
+defm : SelectSetCCZeroRHS<setge, "CMGE">;
+defm : SelectSetCCZeroRHS<setlt, "CMLT">;
+defm : SelectSetCCZeroRHS<setle, "CMLE">;
+
+multiclass SelectSetCCZeroLHS<PatFrags InFrag, string INST> {
+ def : Pat<(v8i8 (InFrag immAllZerosV, (v8i8 V64:$Rn))),
+ (v8i8 (!cast<Instruction>(INST # v8i8rz) (v8i8 V64:$Rn)))>;
+ def : Pat<(v16i8 (InFrag immAllZerosV, (v16i8 V128:$Rn))),
+ (v16i8 (!cast<Instruction>(INST # v16i8rz) (v16i8 V128:$Rn)))>;
+ def : Pat<(v4i16 (InFrag immAllZerosV, (v4i16 V64:$Rn))),
+ (v4i16 (!cast<Instruction>(INST # v4i16rz) (v4i16 V64:$Rn)))>;
+ def : Pat<(v8i16 (InFrag immAllZerosV, (v8i16 V128:$Rn))),
+ (v8i16 (!cast<Instruction>(INST # v8i16rz) (v8i16 V128:$Rn)))>;
+ def : Pat<(v2i32 (InFrag immAllZerosV, (v2i32 V64:$Rn))),
+ (v2i32 (!cast<Instruction>(INST # v2i32rz) (v2i32 V64:$Rn)))>;
+ def : Pat<(v4i32 (InFrag immAllZerosV, (v4i32 V128:$Rn))),
+ (v4i32 (!cast<Instruction>(INST # v4i32rz) (v4i32 V128:$Rn)))>;
+ def : Pat<(v2i64 (InFrag immAllZerosV, (v2i64 V128:$Rn))),
+ (v2i64 (!cast<Instruction>(INST # v2i64rz) (v2i64 V128:$Rn)))>;
+}
+
+defm : SelectSetCCZeroLHS<seteq, "CMEQ">;
+defm : SelectSetCCZeroLHS<setgt, "CMLT">;
+defm : SelectSetCCZeroLHS<setge, "CMLE">;
+defm : SelectSetCCZeroLHS<setlt, "CMGT">;
+defm : SelectSetCCZeroLHS<setle, "CMGE">;
+
let Predicates = [HasNEON] in {
def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
(ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
diff --git a/llvm/test/CodeGen/AArch64/aarch64-addv.ll b/llvm/test/CodeGen/AArch64/aarch64-addv.ll
index ee035ec1941d57..94b792b887eb47 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-addv.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-addv.ll
@@ -94,20 +94,19 @@ define i32 @oversized_ADDV_256(ptr noalias nocapture readonly %arg1, ptr noalias
;
; GISEL-LABEL: oversized_ADDV_256:
; GISEL: // %bb.0: // %entry
-; GISEL-NEXT: ldr d1, [x0]
-; GISEL-NEXT: ldr d2, [x1]
-; GISEL-NEXT: movi v0.2d, #0000000000000000
+; GISEL-NEXT: ldr d0, [x0]
+; GISEL-NEXT: ldr d1, [x1]
+; GISEL-NEXT: ushll v0.8h, v0.8b, #0
; GISEL-NEXT: ushll v1.8h, v1.8b, #0
-; GISEL-NEXT: ushll v2.8h, v2.8b, #0
-; GISEL-NEXT: usubl v3.4s, v1.4h, v2.4h
-; GISEL-NEXT: usubl2 v1.4s, v1.8h, v2.8h
-; GISEL-NEXT: cmgt v2.4s, v0.4s, v3.4s
-; GISEL-NEXT: cmgt v0.4s, v0.4s, v1.4s
-; GISEL-NEXT: neg v4.4s, v3.4s
-; GISEL-NEXT: neg v5.4s, v1.4s
-; GISEL-NEXT: bsl v2.16b, v4.16b, v3.16b
-; GISEL-NEXT: bsl v0.16b, v5.16b, v1.16b
-; GISEL-NEXT: add v0.4s, v2.4s, v0.4s
+; GISEL-NEXT: usubl v2.4s, v0.4h, v1.4h
+; GISEL-NEXT: usubl2 v0.4s, v0.8h, v1.8h
+; GISEL-NEXT: cmlt v1.4s, v2.4s, #0
+; GISEL-NEXT: cmlt v3.4s, v0.4s, #0
+; GISEL-NEXT: neg v4.4s, v2.4s
+; GISEL-NEXT: neg v5.4s, v0.4s
+; GISEL-NEXT: bsl v1.16b, v4.16b, v2.16b
+; GISEL-NEXT: bit v0.16b, v5.16b, v3.16b
+; GISEL-NEXT: add v0.4s, v1.4s, v0.4s
; GISEL-NEXT: addv s0, v0.4s
; GISEL-NEXT: fmov w0, s0
; GISEL-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index d64327656a9e01..f7d31a214563bc 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -252,18 +252,17 @@ define i16 @uabd16b_rdx(ptr %a, ptr %b) {
;
; CHECK-GI-LABEL: uabd16b_rdx:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ldr q1, [x0]
-; CHECK-GI-NEXT: ldr q2, [x1]
-; CHECK-GI-NEXT: movi.2d v0, #0000000000000000
-; CHECK-GI-NEXT: usubl.8h v3, v1, v2
-; CHECK-GI-NEXT: usubl2.8h v1, v1, v2
-; CHECK-GI-NEXT: cmgt.8h v2, v0, v3
-; CHECK-GI-NEXT: cmgt.8h v0, v0, v1
-; CHECK-GI-NEXT: neg.8h v4, v3
-; CHECK-GI-NEXT: neg.8h v5, v1
-; CHECK-GI-NEXT: bsl.16b v2, v4, v3
-; CHECK-GI-NEXT: bsl.16b v0, v5, v1
-; CHECK-GI-NEXT: add.8h v0, v2, v0
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: usubl.8h v2, v0, v1
+; CHECK-GI-NEXT: usubl2.8h v0, v0, v1
+; CHECK-GI-NEXT: cmlt.8h v1, v2, #0
+; CHECK-GI-NEXT: cmlt.8h v3, v0, #0
+; CHECK-GI-NEXT: neg.8h v4, v2
+; CHECK-GI-NEXT: neg.8h v5, v0
+; CHECK-GI-NEXT: bsl.16b v1, v4, v2
+; CHECK-GI-NEXT: bit.16b v0, v5, v3
+; CHECK-GI-NEXT: add.8h v0, v1, v0
; CHECK-GI-NEXT: addv.8h h0, v0
; CHECK-GI-NEXT: fmov w0, s0
; CHECK-GI-NEXT: ret
@@ -290,29 +289,28 @@ define i32 @uabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {
;
; CHECK-GI-LABEL: uabd16b_rdx_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll.8h v3, v0, #0
-; CHECK-GI-NEXT: ushll.8h v4, v1, #0
+; CHECK-GI-NEXT: ushll.8h v2, v0, #0
+; CHECK-GI-NEXT: ushll.8h v3, v1, #0
; CHECK-GI-NEXT: ushll2.8h v0, v0, #0
; CHECK-GI-NEXT: ushll2.8h v1, v1, #0
-; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
-; CHECK-GI-NEXT: usubl.4s v5, v3, v4
-; CHECK-GI-NEXT: usubl2.4s v3, v3, v4
-; CHECK-GI-NEXT: usubl.4s v4, v0, v1
+; CHECK-GI-NEXT: usubl.4s v4, v2, v3
+; CHECK-GI-NEXT: usubl2.4s v2, v2, v3
+; CHECK-GI-NEXT: usubl.4s v3, v0, v1
; CHECK-GI-NEXT: usubl2.4s v0, v0, v1
-; CHECK-GI-NEXT: cmgt.4s v1, v2, v5
-; CHECK-GI-NEXT: cmgt.4s v6, v2, v3
-; CHECK-GI-NEXT: neg.4s v16, v5
-; CHECK-GI-NEXT: cmgt.4s v7, v2, v4
-; CHECK-GI-NEXT: cmgt.4s v2, v2, v0
-; CHECK-GI-NEXT: neg.4s v17, v3
-; CHECK-GI-NEXT: neg.4s v18, v4
+; CHECK-GI-NEXT: cmlt.4s v1, v4, #0
+; CHECK-GI-NEXT: cmlt.4s v5, v2, #0
+; CHECK-GI-NEXT: neg.4s v16, v4
+; CHECK-GI-NEXT: cmlt.4s v6, v3, #0
+; CHECK-GI-NEXT: cmlt.4s v7, v0, #0
+; CHECK-GI-NEXT: neg.4s v17, v2
+; CHECK-GI-NEXT: neg.4s v18, v3
; CHECK-GI-NEXT: neg.4s v19, v0
-; CHECK-GI-NEXT: bsl.16b v1, v16, v5
-; CHECK-GI-NEXT: bit.16b v3, v17, v6
-; CHECK-GI-NEXT: bit.16b v4, v18, v7
-; CHECK-GI-NEXT: bit.16b v0, v19, v2
-; CHECK-GI-NEXT: add.4s v1, v1, v3
-; CHECK-GI-NEXT: add.4s v0, v4, v0
+; CHECK-GI-NEXT: bsl.16b v1, v16, v4
+; CHECK-GI-NEXT: bit.16b v2, v17, v5
+; CHECK-GI-NEXT: bit.16b v3, v18, v6
+; CHECK-GI-NEXT: bit.16b v0, v19, v7
+; CHECK-GI-NEXT: add.4s v1, v1, v2
+; CHECK-GI-NEXT: add.4s v0, v3, v0
; CHECK-GI-NEXT: add.4s v0, v1, v0
; CHECK-GI-NEXT: addv.4s s0, v0
; CHECK-GI-NEXT: fmov w0, s0
@@ -338,29 +336,28 @@ define i32 @sabd16b_rdx_i32(<16 x i8> %a, <16 x i8> %b) {
;
; CHECK-GI-LABEL: sabd16b_rdx_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: sshll.8h v3, v0, #0
-; CHECK-GI-NEXT: sshll.8h v4, v1, #0
+; CHECK-GI-NEXT: sshll.8h v2, v0, #0
+; CHECK-GI-NEXT: sshll.8h v3, v1, #0
; CHECK-GI-NEXT: sshll2.8h v0, v0, #0
; CHECK-GI-NEXT: sshll2.8h v1, v1, #0
-; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
-; CHECK-GI-NEXT: ssubl.4s v5, v3, v4
-; CHECK-GI-NEXT: ssubl2.4s v3, v3, v4
-; CHECK-GI-NEXT: ssubl.4s v4, v0, v1
+; CHECK-GI-NEXT: ssubl.4s v4, v2, v3
+; CHECK-GI-NEXT: ssubl2.4s v2, v2, v3
+; CHECK-GI-NEXT: ssubl.4s v3, v0, v1
; CHECK-GI-NEXT: ssubl2.4s v0, v0, v1
-; CHECK-GI-NEXT: cmgt.4s v1, v2, v5
-; CHECK-GI-NEXT: cmgt.4s v6, v2, v3
-; CHECK-GI-NEXT: neg.4s v16, v5
-; CHECK-GI-NEXT: cmgt.4s v7, v2, v4
-; CHECK-GI-NEXT: cmgt.4s v2, v2, v0
-; CHECK-GI-NEXT: neg.4s v17, v3
-; CHECK-GI-NEXT: neg.4s v18, v4
+; CHECK-GI-NEXT: cmlt.4s v1, v4, #0
+; CHECK-GI-NEXT: cmlt.4s v5, v2, #0
+; CHECK-GI-NEXT: neg.4s v16, v4
+; CHECK-GI-NEXT: cmlt.4s v6, v3, #0
+; CHECK-GI-NEXT: cmlt.4s v7, v0, #0
+; CHECK-GI-NEXT: neg.4s v17, v2
+; CHECK-GI-NEXT: neg.4s v18, v3
; CHECK-GI-NEXT: neg.4s v19, v0
-; CHECK-GI-NEXT: bsl.16b v1, v16, v5
-; CHECK-GI-NEXT: bit.16b v3, v17, v6
-; CHECK-GI-NEXT: bit.16b v4, v18, v7
-; CHECK-GI-NEXT: bit.16b v0, v19, v2
-; CHECK-GI-NEXT: add.4s v1, v1, v3
-; CHECK-GI-NEXT: add.4s v0, v4, v0
+; CHECK-GI-NEXT: bsl.16b v1, v16, v4
+; CHECK-GI-NEXT: bit.16b v2, v17, v5
+; CHECK-GI-NEXT: bit.16b v3, v18, v6
+; CHECK-GI-NEXT: bit.16b v0, v19, v7
+; CHECK-GI-NEXT: add.4s v1, v1, v2
+; CHECK-GI-NEXT: add.4s v0, v3, v0
; CHECK-GI-NEXT: add.4s v0, v1, v0
; CHECK-GI-NEXT: addv.4s s0, v0
; CHECK-GI-NEXT: fmov w0, s0
@@ -391,18 +388,17 @@ define i32 @uabd8h_rdx(ptr %a, ptr %b) {
;
; CHECK-GI-LABEL: uabd8h_rdx:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ldr q1, [x0]
-; CHECK-GI-NEXT: ldr q2, [x1]
-; CHECK-GI-NEXT: movi.2d v0, #0000000000000000
-; CHECK-GI-NEXT: usubl.4s v3, v1, v2
-; CHECK-GI-NEXT: usubl2.4s v1, v1, v2
-; CHECK-GI-NEXT: cmgt.4s v2, v0, v3
-; CHECK-GI-NEXT: cmgt.4s v0, v0, v1
-; CHECK-GI-NEXT: neg.4s v4, v3
-; CHECK-GI-NEXT: neg.4s v5, v1
-; CHECK-GI-NEXT: bsl.16b v2, v4, v3
-; CHECK-GI-NEXT: bsl.16b v0, v5, v1
-; CHECK-GI-NEXT: add.4s v0, v2, v0
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: usubl.4s v2, v0, v1
+; CHECK-GI-NEXT: usubl2.4s v0, v0, v1
+; CHECK-GI-NEXT: cmlt.4s v1, v2, #0
+; CHECK-GI-NEXT: cmlt.4s v3, v0, #0
+; CHECK-GI-NEXT: neg.4s v4, v2
+; CHECK-GI-NEXT: neg.4s v5, v0
+; CHECK-GI-NEXT: bsl.16b v1, v4, v2
+; CHECK-GI-NEXT: bit.16b v0, v5, v3
+; CHECK-GI-NEXT: add.4s v0, v1, v0
; CHECK-GI-NEXT: addv.4s s0, v0
; CHECK-GI-NEXT: fmov w0, s0
; CHECK-GI-NEXT: ret
@@ -428,15 +424,14 @@ define i32 @sabd8h_rdx(<8 x i16> %a, <8 x i16> %b) {
;
; CHECK-GI-LABEL: sabd8h_rdx:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
-; CHECK-GI-NEXT: ssubl.4s v3, v0, v1
+; CHECK-GI-NEXT: ssubl.4s v2, v0, v1
; CHECK-GI-NEXT: ssubl2.4s v0, v0, v1
-; CHECK-GI-NEXT: neg.4s v4, v3
+; CHECK-GI-NEXT: cmlt.4s v1, v2, #0
+; CHECK-GI-NEXT: cmlt.4s v3, v0, #0
+; CHECK-GI-NEXT: neg.4s v4, v2
; CHECK-GI-NEXT: neg.4s v5, v0
-; CHECK-GI-NEXT: cmgt.4s v1, v2, v3
-; CHECK-GI-NEXT: cmgt.4s v2, v2, v0
-; CHECK-GI-NEXT: bsl.16b v1, v4, v3
-; CHECK-GI-NEXT: bit.16b v0, v5, v2
+; CHECK-GI-NEXT: bsl.16b v1, v4, v2
+; CHECK-GI-NEXT: bit.16b v0, v5, v3
; CHECK-GI-NEXT: add.4s v0, v1, v0
; CHECK-GI-NEXT: addv.4s s0, v0
; CHECK-GI-NEXT: fmov w0, s0
@@ -461,9 +456,8 @@ define i32 @uabdl4s_rdx_i32(<4 x i16> %a, <4 x i16> %b) {
;
; CHECK-GI-LABEL: uabdl4s_rdx_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
; CHECK-GI-NEXT: usubl.4s v0, v0, v1
-; CHECK-GI-NEXT: cmgt.4s v1, v2, v0
+; CHECK-GI-NEXT: cmlt.4s v1, v0, #0
; CHECK-GI-NEXT: neg.4s v2, v0
; CHECK-GI-NEXT: bit.16b v0, v2, v1
; CHECK-GI-NEXT: addv.4s s0, v0
@@ -494,18 +488,17 @@ define i64 @uabd4s_rdx(ptr %a, ptr %b, i32 %h) {
;
; CHECK-GI-LABEL: uabd4s_rdx:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ldr q1, [x0]
-; CHECK-GI-NEXT: ldr q2, [x1]
-; CHECK-GI-NEXT: movi.2d v0, #0000000000000000
-; CHECK-GI-NEXT: usubl.2d v3, v1, v2
-; CHECK-GI-NEXT: usubl2.2d v1, v1, v2
-; CHECK-GI-NEXT: cmgt.2d v2, v0, v3
-; CHECK-GI-NEXT: cmgt.2d v0, v0, v1
-; CHECK-GI-NEXT: neg.2d v4, v3
-; CHECK-GI-NEXT: neg.2d v5, v1
-; CHECK-GI-NEXT: bsl.16b v2, v4, v3
-; CHECK-GI-NEXT: bsl.16b v0, v5, v1
-; CHECK-GI-NEXT: add.2d v0, v2, v0
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: usubl.2d v2, v0, v1
+; CHECK-GI-NEXT: usubl2.2d v0, v0, v1
+; CHECK-GI-NEXT: cmlt.2d v1, v2, #0
+; CHECK-GI-NEXT: cmlt.2d v3, v0, #0
+; CHECK-GI-NEXT: neg.2d v4, v2
+; CHECK-GI-NEXT: neg.2d v5, v0
+; CHECK-GI-NEXT: bsl.16b v1, v4, v2
+; CHECK-GI-NEXT: bit.16b v0, v5, v3
+; CHECK-GI-NEXT: add.2d v0, v1, v0
; CHECK-GI-NEXT: addp.2d d0, v0
; CHECK-GI-NEXT: fmov x0, d0
; CHECK-GI-NEXT: ret
@@ -531,15 +524,14 @@ define i64 @sabd4s_rdx(<4 x i32> %a, <4 x i32> %b) {
;
; CHECK-GI-LABEL: sabd4s_rdx:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
-; CHECK-GI-NEXT: ssubl.2d v3, v0, v1
+; CHECK-GI-NEXT: ssubl.2d v2, v0, v1
; CHECK-GI-NEXT: ssubl2.2d v0, v0, v1
-; CHECK-GI-NEXT: neg.2d v4, v3
+; CHECK-GI-NEXT: cmlt.2d v1, v2, #0
+; CHECK-GI-NEXT: cmlt.2d v3, v0, #0
+; CHECK-GI-NEXT: neg.2d v4, v2
; CHECK-GI-NEXT: neg.2d v5, v0
-; CHECK-GI-NEXT: cmgt.2d v1, v2, v3
-; CHECK-GI-NEXT: cmgt.2d v2, v2, v0
-; CHECK-GI-NEXT: bsl.16b v1, v4, v3
-; CHECK-GI-NEXT: bit.16b v0, v5, v2
+; CHECK-GI-NEXT: bsl.16b v1, v4, v2
+; CHECK-GI-NEXT: bit.16b v0, v5, v3
; CHECK-GI-NEXT: add.2d v0, v1, v0
; CHECK-GI-NEXT: addp.2d d0, v0
; CHECK-GI-NEXT: fmov x0, d0
@@ -564,9 +556,8 @@ define i64 @uabdl2d_rdx_i64(<2 x i32> %a, <2 x i32> %b) {
;
; CHECK-GI-LABEL: uabdl2d_rdx_i64:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
; CHECK-GI-NEXT: usubl.2d v0, v0, v1
-; CHECK-GI-NEXT: cmgt.2d v1, v2, v0
+; CHECK-GI-NEXT: cmlt.2d v1, v0, #0
; CHECK-GI-NEXT: neg.2d v2, v0
; CHECK-GI-NEXT: bit.16b v0, v2, v1
; CHECK-GI-NEXT: addp.2d d0, v0
@@ -1662,10 +1653,9 @@ define <2 x i32> @abspattern1(<2 x i32> %a) nounwind {
;
; CHECK-GI-LABEL: abspattern1:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
-; CHECK-GI-NEXT: neg.2s v2, v0
-; CHECK-GI-NEXT: cmge.2s v1, v0, v1
-; CHECK-GI-NEXT: bif.8b v0, v2, v1
+; CHECK-GI-NEXT: neg.2s v1, v0
+; CHECK-GI-NEXT: cmge.2s v2, v0, #0
+; CHECK-GI-NEXT: bif.8b v0, v1, v2
; CHECK-GI-NEXT: ret
%tmp1neg = sub <2 x i32> zeroinitializer, %a
%b = icmp sge <2 x i32> %a, zeroinitializer
@@ -1682,10 +1672,9 @@ define <4 x i16> @abspattern2(<4 x i16> %a) nounwind {
;
; CHECK-GI-LABEL: abspattern2:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
-; CHECK-GI-NEXT: neg.4h v2, v0
-; CHECK-GI-NEXT: cmgt.4h v1, v0, v1
-; CHECK-GI-NEXT: bif.8b v0, v2, v1
+; CHECK-GI-NEXT: neg.4h v1, v0
+; CHECK-GI-NEXT: cmgt.4h v2, v0, #0
+; CHECK-GI-NEXT: bif.8b v0, v1, v2
; CHECK-GI-NEXT: ret
%tmp1neg = sub <4 x i16> zeroinitializer, %a
%b = icmp sgt <4 x i16> %a, zeroinitializer
@@ -1701,10 +1690,9 @@ define <8 x i8> @abspattern3(<8 x i8> %a) nounwind {
;
; CHECK-GI-LABEL: abspattern3:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
-; CHECK-GI-NEXT: neg.8b v2, v0
-; CHECK-GI-NEXT: cmgt.8b v1, v1, v0
-; CHECK-GI-NEXT: bit.8b v0, v2, v1
+; CHECK-GI-NEXT: neg.8b v1, v0
+; CHECK-GI-NEXT: cmlt.8b v2, v0, #0
+; CHECK-GI-NEXT: bit.8b v0, v1, v2
; CHECK-GI-NEXT: ret
%tmp1neg = sub <8 x i8> zeroinitializer, %a
%b = icmp slt <8 x i8> %a, zeroinitializer
@@ -1720,10 +1708,9 @@ define <4 x i32> @abspattern4(<4 x i32> %a) nounwind {
;
; CHECK-GI-LABEL: abspattern4:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
-; CHECK-GI-NEXT: neg.4s v2, v0
-; CHECK-GI-NEXT: cmge.4s v1, v0, v1
-; CHECK-GI-NEXT: bif.16b v0, v2, v1
+; CHECK-GI-NEXT: neg.4s v1, v0
+; CHECK-GI-NEXT: cmge.4s v2, v0, #0
+; CHECK-GI-NEXT: bif.16b v0, v1, v2
; CHECK-GI-NEXT: ret
%tmp1neg = sub <4 x i32> zeroinitializer, %a
%b = icmp sge <4 x i32> %a, zeroinitializer
@@ -1739,10 +1726,9 @@ define <8 x i16> @abspattern5(<8 x i16> %a) nounwind {
;
; CHECK-GI-LABEL: abspattern5:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
-; CHECK-GI-NEXT: neg.8h v2, v0
-; CHECK-GI-NEXT: cmgt.8h v1, v0, v1
-; CHECK-GI-NEXT: bif.16b v0, v2, v1
+; CHECK-GI-NEXT: neg.8h v1, v0
+; CHECK-GI-NEXT: cmgt.8h v2, v0, #0
+; CHECK-GI-NEXT: bif.16b v0, v1, v2
; CHECK-GI-NEXT: ret
%tmp1neg = sub <8 x i16> zeroinitializer, %a
%b = icmp sgt <8 x i16> %a, zeroinitializer
@@ -1758,10 +1744,9 @@ define <16 x i8> @abspattern6(<16 x i8> %a) nounwind {
;
; CHECK-GI-LABEL: abspattern6:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
-; CHECK-GI-NEXT: neg.16b v2, v0
-; CHECK-GI-NEXT: cmgt.16b v1, v1, v0
-; CHECK-GI-NEXT: bit.16b v0, v2, v1
+; CHECK-GI-NEXT: neg.16b v1, v0
+; CHECK-GI-NEXT: cmlt.16b v2, v0, #0
+; CHECK-GI-NEXT: bit.16b v0, v1, v2
; CHECK-GI-NEXT: ret
%tmp1neg = sub <16 x i8> zeroinitializer, %a
%b = icmp slt <16 x i8> %a, zeroinitializer
@@ -1777,10 +1762,9 @@ define <2 x i64> @abspattern7(<2 x i64> %a) nounwind {
;
; CHECK-GI-LABEL: abspattern7:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
-; CHECK-GI-NEXT: neg.2d v2, v0
-; CHECK-GI-NEXT: cmge.2d v1, v1, v0
-; CHECK-GI-NEXT: bit.16b v0, v2, v1
+; CHECK-GI-NEXT: neg.2d v1, v0
+; CHECK-GI-NEXT: cmle.2d v2, v0, #0
+; CHECK-GI-NEXT: bit.16b v0, v1, v2
; CHECK-GI-NEXT: ret
%tmp1neg = sub <2 x i64> zeroinitializer, %a
%b = icmp sle <2 x i64> %a, zeroinitializer
@@ -1796,9 +1780,8 @@ define <2 x i64> @uabd_i32(<2 x i32> %a, <2 x i32> %b) {
;
; CHECK-GI-LABEL: uabd_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
; CHECK-GI-NEXT: ssubl.2d v0, v0, v1
-; CHECK-GI-NEXT: cmgt.2d v1, v2, v0
+; CHECK-GI-NEXT: cmlt.2d v1, v0, #0
; CHECK-GI-NEXT: neg.2d v2, v0
; CHECK-GI-NEXT: bit.16b v0, v2, v1
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/icmp.ll b/llvm/test/CodeGen/AArch64/icmp.ll
index de1a45204836cc..06e69572bc5779 100644
--- a/llvm/test/CodeGen/AArch64/icmp.ll
+++ b/llvm/test/CodeGen/AArch64/icmp.ll
@@ -323,556 +323,331 @@ entry:
; ===== ICMP Zero RHS =====
define <8 x i1> @icmp_eq_v8i8_Zero_RHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_eq_v8i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v8i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v8i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp eq <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <8 x i1> %c
}
define <16 x i1> @icmp_eq_v16i8_Zero_RHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_eq_v16i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v16i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v16i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp eq <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <16 x i1> %c
}
define <4 x i1> @icmp_eq_v4i16_Zero_RHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_eq_v4i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v4i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v4i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp eq <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
ret <4 x i1> %c
}
define <8 x i1> @icmp_eq_v8i16_Zero_RHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_eq_v8i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v8i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v8i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp eq <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
ret <8 x i1> %c
}
define <2 x i1> @icmp_eq_v2i32_Zero_RHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_eq_v2i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v2i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v2i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp eq <2 x i32> %a, <i32 0, i32 0>
ret <2 x i1> %c
}
define <4 x i1> @icmp_eq_v4i32_Zero_RHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_eq_v4i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v4i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v4i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp eq <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
ret <4 x i1> %c
}
define <2 x i1> @icmp_eq_v2i64_Zero_RHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_eq_v2i64_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v2i64_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v2i64_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp eq <2 x i64> %a, <i64 0, i64 0>
ret <2 x i1> %c
}
define <8 x i1> @icmp_sge_v8i8_Zero_RHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sge_v8i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v8i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v8i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp sge <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <8 x i1> %c
}
define <16 x i1> @icmp_sge_v16i8_Zero_RHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sge_v16i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v16i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v16i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp sge <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <16 x i1> %c
}
define <4 x i1> @icmp_sge_v4i16_Zero_RHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sge_v4i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v4i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v4i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp sge <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
ret <4 x i1> %c
}
define <8 x i1> @icmp_sge_v8i16_Zero_RHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sge_v8i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v8i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v8i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp sge <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
ret <8 x i1> %c
}
define <2 x i1> @icmp_sge_v2i32_Zero_RHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sge_v2i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v2i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v2i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp sge <2 x i32> %a, <i32 0, i32 0>
ret <2 x i1> %c
}
define <4 x i1> @icmp_sge_v4i32_Zero_RHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sge_v4i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v4i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v4i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp sge <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
ret <4 x i1> %c
}
define <2 x i1> @icmp_sge_v2i64_Zero_RHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_sge_v2i64_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v2i64_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v2i64_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp sge <2 x i64> %a, <i64 0, i64 0>
ret <2 x i1> %c
}
define <8 x i1> @icmp_sgt_v8i8_Zero_RHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v8i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v8i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v8i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp sgt <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <8 x i1> %c
}
define <16 x i1> @icmp_sgt_v16i8_Zero_RHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v16i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v16i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v16i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp sgt <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <16 x i1> %c
}
define <4 x i1> @icmp_sgt_v4i16_Zero_RHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v4i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v4i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v4i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp sgt <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
ret <4 x i1> %c
}
define <8 x i1> @icmp_sgt_v8i16_Zero_RHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v8i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v8i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v8i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp sgt <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
ret <8 x i1> %c
}
define <2 x i1> @icmp_sgt_v2i32_Zero_RHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v2i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v2i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v2i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp sgt <2 x i32> %a, <i32 0, i32 0>
ret <2 x i1> %c
}
define <4 x i1> @icmp_sgt_v4i32_Zero_RHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v4i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v4i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v4i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp sgt <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
ret <4 x i1> %c
}
define <2 x i1> @icmp_sgt_v2i64_Zero_RHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v2i64_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v2i64_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v2i64_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp sgt <2 x i64> %a, <i64 0, i64 0>
ret <2 x i1> %c
}
define <8 x i1> @icmp_sle_v8i8_Zero_RHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sle_v8i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v8i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v8i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp sle <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <8 x i1> %c
}
define <16 x i1> @icmp_sle_v16i8_Zero_RHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sle_v16i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v16i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v16i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp sle <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <16 x i1> %c
}
define <4 x i1> @icmp_sle_v4i16_Zero_RHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sle_v4i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v4i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v4i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp sle <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
ret <4 x i1> %c
}
define <8 x i1> @icmp_sle_v8i16_Zero_RHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sle_v8i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v8i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8h, v1.8h, v0.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v8i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp sle <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
ret <8 x i1> %c
}
define <2 x i1> @icmp_sle_v2i32_Zero_RHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sle_v2i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v2i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2s, v1.2s, v0.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v2i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp sle <2 x i32> %a, <i32 0, i32 0>
ret <2 x i1> %c
}
define <4 x i1> @icmp_sle_v4i32_Zero_RHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sle_v4i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v4i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v4i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp sle <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
ret <4 x i1> %c
}
define <2 x i1> @icmp_sle_v2i64_Zero_RHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_sle_v2i64_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v2i64_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v2i64_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp sle <2 x i64> %a, <i64 0, i64 0>
ret <2 x i1> %c
}
define <8 x i1> @icmp_slt_v8i8_Zero_RHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_slt_v8i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v8i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v8i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp slt <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <8 x i1> %c
}
define <16 x i1> @icmp_slt_v16i8_Zero_RHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_slt_v16i8_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v16i8_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v16i8_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp slt <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
ret <16 x i1> %c
}
define <4 x i1> @icmp_slt_v4i16_Zero_RHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_slt_v4i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v4i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v4i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp slt <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>
ret <4 x i1> %c
}
define <8 x i1> @icmp_slt_v8i16_Zero_RHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_slt_v8i16_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v8i16_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v8i16_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp slt <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
ret <8 x i1> %c
}
define <2 x i1> @icmp_slt_v2i32_Zero_RHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_slt_v2i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v2i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2s, v1.2s, v0.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v2i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp slt <2 x i32> %a, <i32 0, i32 0>
ret <2 x i1> %c
}
define <4 x i1> @icmp_slt_v4i32_Zero_RHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_slt_v4i32_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v4i32_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v4i32_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp slt <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>
ret <4 x i1> %c
}
define <2 x i1> @icmp_slt_v2i64_Zero_RHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_slt_v2i64_Zero_RHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v2i64_Zero_RHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v2i64_Zero_RHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp slt <2 x i64> %a, <i64 0, i64 0>
ret <2 x i1> %c
}
@@ -880,556 +655,331 @@ define <2 x i1> @icmp_slt_v2i64_Zero_RHS(<2 x i64> %a) {
; ===== ICMP Zero LHS =====
define <8 x i1> @icmp_eq_v8i8_Zero_LHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_eq_v8i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v8i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v8i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp eq <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <8 x i1> %c
}
define <16 x i1> @icmp_eq_v16i8_Zero_LHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_eq_v16i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v16i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v16i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp eq <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <16 x i1> %c
}
define <4 x i1> @icmp_eq_v4i16_Zero_LHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_eq_v4i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v4i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v4i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp eq <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
ret <4 x i1> %c
}
define <8 x i1> @icmp_eq_v8i16_Zero_LHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_eq_v8i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v8i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8h, v1.8h, v0.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v8i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp eq <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
ret <8 x i1> %c
}
define <2 x i1> @icmp_eq_v2i32_Zero_LHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_eq_v2i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v2i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.2s, v1.2s, v0.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v2i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp eq <2 x i32> <i32 0, i32 0>, %a
ret <2 x i1> %c
}
define <4 x i1> @icmp_eq_v4i32_Zero_LHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_eq_v4i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v4i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v4i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp eq <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
ret <4 x i1> %c
}
define <2 x i1> @icmp_eq_v2i64_Zero_LHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_eq_v2i64_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_eq_v2i64_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_eq_v2i64_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp eq <2 x i64> <i64 0, i64 0>, %a
ret <2 x i1> %c
}
define <8 x i1> @icmp_sge_v8i8_Zero_LHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sge_v8i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v8i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v8i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp sge <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <8 x i1> %c
}
define <16 x i1> @icmp_sge_v16i8_Zero_LHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sge_v16i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v16i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v16i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp sge <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <16 x i1> %c
}
define <4 x i1> @icmp_sge_v4i16_Zero_LHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sge_v4i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v4i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v4i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp sge <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
ret <4 x i1> %c
}
define <8 x i1> @icmp_sge_v8i16_Zero_LHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sge_v8i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v8i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8h, v1.8h, v0.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v8i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp sge <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
ret <8 x i1> %c
}
define <2 x i1> @icmp_sge_v2i32_Zero_LHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sge_v2i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v2i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2s, v1.2s, v0.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v2i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp sge <2 x i32> <i32 0, i32 0>, %a
ret <2 x i1> %c
}
define <4 x i1> @icmp_sge_v4i32_Zero_LHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sge_v4i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v4i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v4i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp sge <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
ret <4 x i1> %c
}
define <2 x i1> @icmp_sge_v2i64_Zero_LHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_sge_v2i64_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sge_v2i64_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sge_v2i64_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp sge <2 x i64> <i64 0, i64 0>, %a
ret <2 x i1> %c
}
define <8 x i1> @icmp_sgt_v8i8_Zero_LHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v8i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v8i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v8i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp sgt <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <8 x i1> %c
}
define <16 x i1> @icmp_sgt_v16i8_Zero_LHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v16i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v16i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v16i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp sgt <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <16 x i1> %c
}
define <4 x i1> @icmp_sgt_v4i16_Zero_LHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v4i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v4i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v4i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp sgt <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
ret <4 x i1> %c
}
define <8 x i1> @icmp_sgt_v8i16_Zero_LHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v8i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v8i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v8i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp sgt <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
ret <8 x i1> %c
}
define <2 x i1> @icmp_sgt_v2i32_Zero_LHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v2i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v2i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2s, v1.2s, v0.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v2i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp sgt <2 x i32> <i32 0, i32 0>, %a
ret <2 x i1> %c
}
define <4 x i1> @icmp_sgt_v4i32_Zero_LHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v4i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v4i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v4i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp sgt <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
ret <4 x i1> %c
}
define <2 x i1> @icmp_sgt_v2i64_Zero_LHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_sgt_v2i64_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sgt_v2i64_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sgt_v2i64_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp sgt <2 x i64> <i64 0, i64 0>, %a
ret <2 x i1> %c
}
define <8 x i1> @icmp_sle_v8i8_Zero_LHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sle_v8i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v8i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v8i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp sle <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <8 x i1> %c
}
define <16 x i1> @icmp_sle_v16i8_Zero_LHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_sle_v16i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v16i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v16i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp sle <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <16 x i1> %c
}
define <4 x i1> @icmp_sle_v4i16_Zero_LHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sle_v4i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v4i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v4i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp sle <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
ret <4 x i1> %c
}
define <8 x i1> @icmp_sle_v8i16_Zero_LHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_sle_v8i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v8i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v8i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp sle <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
ret <8 x i1> %c
}
define <2 x i1> @icmp_sle_v2i32_Zero_LHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sle_v2i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v2i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v2i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp sle <2 x i32> <i32 0, i32 0>, %a
ret <2 x i1> %c
}
define <4 x i1> @icmp_sle_v4i32_Zero_LHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_sle_v4i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v4i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v4i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp sle <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
ret <4 x i1> %c
}
define <2 x i1> @icmp_sle_v2i64_Zero_LHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_sle_v2i64_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_sle_v2i64_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_sle_v2i64_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp sle <2 x i64> <i64 0, i64 0>, %a
ret <2 x i1> %c
}
define <8 x i1> @icmp_slt_v8i8_Zero_LHS(<8 x i8> %a) {
-; CHECK-SD-LABEL: icmp_slt_v8i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v8i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v8i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%c = icmp slt <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <8 x i1> %c
}
define <16 x i1> @icmp_slt_v16i8_Zero_LHS(<16 x i8> %a) {
-; CHECK-SD-LABEL: icmp_slt_v16i8_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v16i8_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v16i8_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%c = icmp slt <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a
ret <16 x i1> %c
}
define <4 x i1> @icmp_slt_v4i16_Zero_LHS(<4 x i16> %a) {
-; CHECK-SD-LABEL: icmp_slt_v4i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v4i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v4i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%c = icmp slt <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a
ret <4 x i1> %c
}
define <8 x i1> @icmp_slt_v8i16_Zero_LHS(<8 x i16> %a) {
-; CHECK-SD-LABEL: icmp_slt_v8i16_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: xtn v0.8b, v0.8h
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v8i16_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: xtn v0.8b, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v8i16_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8h, v0.8h, #0
+; CHECK-NEXT: xtn v0.8b, v0.8h
+; CHECK-NEXT: ret
%c = icmp slt <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a
ret <8 x i1> %c
}
define <2 x i1> @icmp_slt_v2i32_Zero_LHS(<2 x i32> %a) {
-; CHECK-SD-LABEL: icmp_slt_v2i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v2i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v2i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%c = icmp slt <2 x i32> <i32 0, i32 0>, %a
ret <2 x i1> %c
}
define <4 x i1> @icmp_slt_v4i32_Zero_LHS(<4 x i32> %a) {
-; CHECK-SD-LABEL: icmp_slt_v4i32_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: xtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v4i32_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v4i32_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4s, v0.4s, #0
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%c = icmp slt <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a
ret <4 x i1> %c
}
define <2 x i1> @icmp_slt_v2i64_Zero_LHS(<2 x i64> %a) {
-; CHECK-SD-LABEL: icmp_slt_v2i64_Zero_LHS:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: icmp_slt_v2i64_Zero_LHS:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: icmp_slt_v2i64_Zero_LHS:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.2d, v0.2d, #0
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: ret
%c = icmp slt <2 x i64> <i64 0, i64 0>, %a
ret <2 x i1> %c
}
diff --git a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
index 57f220f621cf8b..28b5603dd53f6d 100644
--- a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
@@ -1524,38 +1524,23 @@ define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
}
define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
-; CHECK-SD-LABEL: vselect_cmpz_eq:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: bsl v0.8b, v1.8b, v2.8b
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vselect_cmpz_eq:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v3.8b
-; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vselect_cmpz_eq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: ret
%cmp = icmp eq <8 x i8> %a, zeroinitializer
%d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
ret <8 x i8> %d
}
define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
-; CHECK-SD-LABEL: vselect_tst:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: bsl v0.8b, v2.8b, v1.8b
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: vselect_tst:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
-; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v3.8b
-; CHECK-GI-NEXT: bsl v0.8b, v2.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: vselect_tst:
+; CHECK: // %bb.0:
+; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-NEXT: bsl v0.8b, v2.8b, v1.8b
+; CHECK-NEXT: ret
%tmp3 = and <8 x i8> %a, %b
%tmp4 = icmp eq <8 x i8> %tmp3, zeroinitializer
%d = select <8 x i1> %tmp4, <8 x i8> %c, <8 x i8> %b
diff --git a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
index dbb5dfebd44abc..5da672cb1c1ae2 100644
--- a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll
@@ -873,112 +873,70 @@ define <2 x i64> @cmtst2xi64(<2 x i64> %A, <2 x i64> %B) {
define <8 x i8> @cmeqz8xi8(<8 x i8> %A) {
-; CHECK-SD-LABEL: cmeqz8xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmeqz8xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmeqz8xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp eq <8 x i8> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <16 x i8> @cmeqz16xi8(<16 x i8> %A) {
-; CHECK-SD-LABEL: cmeqz16xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmeqz16xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmeqz16xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp eq <16 x i8> %A, zeroinitializer
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
define <4 x i16> @cmeqz4xi16(<4 x i16> %A) {
-; CHECK-SD-LABEL: cmeqz4xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmeqz4xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmeqz4xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp eq <4 x i16> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
define <8 x i16> @cmeqz8xi16(<8 x i16> %A) {
-; CHECK-SD-LABEL: cmeqz8xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmeqz8xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmeqz8xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.8h, v0.8h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp eq <8 x i16> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
define <2 x i32> @cmeqz2xi32(<2 x i32> %A) {
-; CHECK-SD-LABEL: cmeqz2xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmeqz2xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmeqz2xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp eq <2 x i32> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <4 x i32> @cmeqz4xi32(<4 x i32> %A) {
-; CHECK-SD-LABEL: cmeqz4xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmeqz4xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmeqz4xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp eq <4 x i32> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <2 x i64> @cmeqz2xi64(<2 x i64> %A) {
-; CHECK-SD-LABEL: cmeqz2xi64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmeqz2xi64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmeqz2xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmeq v0.2d, v0.2d, #0
+; CHECK-NEXT: ret
%tmp3 = icmp eq <2 x i64> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4
@@ -986,112 +944,70 @@ define <2 x i64> @cmeqz2xi64(<2 x i64> %A) {
define <8 x i8> @cmgez8xi8(<8 x i8> %A) {
-; CHECK-SD-LABEL: cmgez8xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgez8xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgez8xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sge <8 x i8> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <16 x i8> @cmgez16xi8(<16 x i8> %A) {
-; CHECK-SD-LABEL: cmgez16xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgez16xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgez16xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sge <16 x i8> %A, zeroinitializer
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
define <4 x i16> @cmgez4xi16(<4 x i16> %A) {
-; CHECK-SD-LABEL: cmgez4xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgez4xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgez4xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sge <4 x i16> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
define <8 x i16> @cmgez8xi16(<8 x i16> %A) {
-; CHECK-SD-LABEL: cmgez8xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgez8xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgez8xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.8h, v0.8h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sge <8 x i16> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
define <2 x i32> @cmgez2xi32(<2 x i32> %A) {
-; CHECK-SD-LABEL: cmgez2xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgez2xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgez2xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sge <2 x i32> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <4 x i32> @cmgez4xi32(<4 x i32> %A) {
-; CHECK-SD-LABEL: cmgez4xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgez4xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgez4xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.4s, v0.4s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sge <4 x i32> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <2 x i64> @cmgez2xi64(<2 x i64> %A) {
-; CHECK-SD-LABEL: cmgez2xi64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmge v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgez2xi64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgez2xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmge v0.2d, v0.2d, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sge <2 x i64> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4
@@ -1324,224 +1240,140 @@ define <2 x i64> @cmgez2xi64_alt2(<2 x i64> %A) {
define <8 x i8> @cmgtz8xi8(<8 x i8> %A) {
-; CHECK-SD-LABEL: cmgtz8xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgtz8xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgtz8xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sgt <8 x i8> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <16 x i8> @cmgtz16xi8(<16 x i8> %A) {
-; CHECK-SD-LABEL: cmgtz16xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgtz16xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgtz16xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sgt <16 x i8> %A, zeroinitializer
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
define <4 x i16> @cmgtz4xi16(<4 x i16> %A) {
-; CHECK-SD-LABEL: cmgtz4xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgtz4xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgtz4xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sgt <4 x i16> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
define <8 x i16> @cmgtz8xi16(<8 x i16> %A) {
-; CHECK-SD-LABEL: cmgtz8xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgtz8xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgtz8xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.8h, v0.8h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sgt <8 x i16> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
define <2 x i32> @cmgtz2xi32(<2 x i32> %A) {
-; CHECK-SD-LABEL: cmgtz2xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgtz2xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2s, v0.2s, v1.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgtz2xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sgt <2 x i32> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <4 x i32> @cmgtz4xi32(<4 x i32> %A) {
-; CHECK-SD-LABEL: cmgtz4xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgtz4xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgtz4xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.4s, v0.4s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sgt <4 x i32> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <2 x i64> @cmgtz2xi64(<2 x i64> %A) {
-; CHECK-SD-LABEL: cmgtz2xi64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmgt v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmgtz2xi64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2d, v0.2d, v1.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmgtz2xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmgt v0.2d, v0.2d, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sgt <2 x i64> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4
}
define <8 x i8> @cmlez8xi8(<8 x i8> %A) {
-; CHECK-SD-LABEL: cmlez8xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmlez8xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmlez8xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sle <8 x i8> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <16 x i8> @cmlez16xi8(<16 x i8> %A) {
-; CHECK-SD-LABEL: cmlez16xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmlez16xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmlez16xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sle <16 x i8> %A, zeroinitializer
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
define <4 x i16> @cmlez4xi16(<4 x i16> %A) {
-; CHECK-SD-LABEL: cmlez4xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmlez4xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmlez4xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sle <4 x i16> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
define <8 x i16> @cmlez8xi16(<8 x i16> %A) {
-; CHECK-SD-LABEL: cmlez8xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmlez8xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.8h, v1.8h, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmlez8xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.8h, v0.8h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sle <8 x i16> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
define <2 x i32> @cmlez2xi32(<2 x i32> %A) {
-; CHECK-SD-LABEL: cmlez2xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmlez2xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2s, v1.2s, v0.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmlez2xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sle <2 x i32> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <4 x i32> @cmlez4xi32(<4 x i32> %A) {
-; CHECK-SD-LABEL: cmlez4xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmlez4xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmlez4xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.4s, v0.4s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sle <4 x i32> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <2 x i64> @cmlez2xi64(<2 x i64> %A) {
-; CHECK-SD-LABEL: cmlez2xi64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmle v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmlez2xi64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmge v0.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmlez2xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmle v0.2d, v0.2d, #0
+; CHECK-NEXT: ret
%tmp3 = icmp sle <2 x i64> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4
@@ -1661,112 +1493,70 @@ define <2 x i64> @cmlez2xi64_alt(<2 x i64> %A) {
}
define <8 x i8> @cmltz8xi8(<8 x i8> %A) {
-; CHECK-SD-LABEL: cmltz8xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.8b, v0.8b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmltz8xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmltz8xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp slt <8 x i8> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
ret <8 x i8> %tmp4
}
define <16 x i8> @cmltz16xi8(<16 x i8> %A) {
-; CHECK-SD-LABEL: cmltz16xi8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmltz16xi8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmltz16xi8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
+; CHECK-NEXT: ret
%tmp3 = icmp slt <16 x i8> %A, zeroinitializer
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
ret <16 x i8> %tmp4
}
define <4 x i16> @cmltz4xi16(<4 x i16> %A) {
-; CHECK-SD-LABEL: cmltz4xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmltz4xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmltz4xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.4h, v0.4h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp slt <4 x i16> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
ret <4 x i16> %tmp4
}
define <8 x i16> @cmltz8xi16(<8 x i16> %A) {
-; CHECK-SD-LABEL: cmltz8xi16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.8h, v0.8h, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmltz8xi16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmltz8xi16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.8h, v0.8h, #0
+; CHECK-NEXT: ret
%tmp3 = icmp slt <8 x i16> %A, zeroinitializer
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
ret <8 x i16> %tmp4
}
define <2 x i32> @cmltz2xi32(<2 x i32> %A) {
-; CHECK-SD-LABEL: cmltz2xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmltz2xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2s, v1.2s, v0.2s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmltz2xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.2s, v0.2s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp slt <2 x i32> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
ret <2 x i32> %tmp4
}
define <4 x i32> @cmltz4xi32(<4 x i32> %A) {
-; CHECK-SD-LABEL: cmltz4xi32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmltz4xi32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmltz4xi32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.4s, v0.4s, #0
+; CHECK-NEXT: ret
%tmp3 = icmp slt <4 x i32> %A, zeroinitializer
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
ret <4 x i32> %tmp4
}
define <2 x i64> @cmltz2xi64(<2 x i64> %A) {
-; CHECK-SD-LABEL: cmltz2xi64:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: cmlt v0.2d, v0.2d, #0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: cmltz2xi64:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
-; CHECK-GI-NEXT: cmgt v0.2d, v1.2d, v0.2d
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: cmltz2xi64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmlt v0.2d, v0.2d, #0
+; CHECK-NEXT: ret
%tmp3 = icmp slt <2 x i64> %A, zeroinitializer
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
ret <2 x i64> %tmp4
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