[llvm] [NFC][RISCV] Keep AVLReg define instr inside VSETVLInfo (PR #89180)
Piyou Chen via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 24 23:13:03 PDT 2024
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/89180
>From 882a1bbff1b2973e34a5256687c15414a36857d7 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Thu, 25 Apr 2024 01:51:21 +0800
Subject: [PATCH 1/5] [RISCV] Split out VSETVLIInfo AVL states to be more
explicit
We currently use AVLIsReg to represent VLMAX as well as a dummy value for
whenever the VL is ignored by vmv.x.s. This splits them out into separate
states so that AVLIsReg is always a virtual register and should help with
tracking the definition inside VSETVLIInfo directly in #89180.
This is almost an NFC but it sets the kill flag for x0 in more places.
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 133 ++++++++++--------
.../RISCV/rvv/vsetvli-insert-crossbb.mir | 12 +-
.../test/CodeGen/RISCV/rvv/vsetvli-insert.mir | 20 +--
3 files changed, 94 insertions(+), 71 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index ec1a9f4c135ccb..1a73e6c5700b85 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -452,6 +452,8 @@ class VSETVLIInfo {
Uninitialized,
AVLIsReg,
AVLIsImm,
+ AVLIsVLMAX,
+ AVLIsIgnored,
Unknown,
} State = Uninitialized;
@@ -478,7 +480,7 @@ class VSETVLIInfo {
bool isUnknown() const { return State == Unknown; }
void setAVLReg(Register Reg) {
- assert(Reg.isVirtual() || Reg == RISCV::X0 || Reg == RISCV::NoRegister);
+ assert(Reg.isVirtual());
AVLReg = Reg;
State = AVLIsReg;
}
@@ -488,8 +490,14 @@ class VSETVLIInfo {
State = AVLIsImm;
}
+ void setAVLVLMAX() { State = AVLIsVLMAX; }
+
+ void setAVLIgnored() { State = AVLIsIgnored; }
+
bool hasAVLImm() const { return State == AVLIsImm; }
bool hasAVLReg() const { return State == AVLIsReg; }
+ bool hasAVLVLMAX() const { return State == AVLIsVLMAX; }
+ bool hasAVLIgnored() const { return State == AVLIsIgnored; }
Register getAVLReg() const {
assert(hasAVLReg());
return AVLReg;
@@ -505,6 +513,10 @@ class VSETVLIInfo {
setUnknown();
else if (Info.hasAVLReg())
setAVLReg(Info.getAVLReg());
+ else if (Info.hasAVLVLMAX())
+ setAVLVLMAX();
+ else if (Info.hasAVLIgnored())
+ setAVLIgnored();
else {
assert(Info.hasAVLImm());
setAVLImm(Info.getAVLImm());
@@ -520,13 +532,14 @@ class VSETVLIInfo {
if (hasAVLImm())
return getAVLImm() > 0;
if (hasAVLReg()) {
- if (getAVLReg() == RISCV::X0)
- return true;
- if (MachineInstr *MI = MRI.getVRegDef(getAVLReg());
- MI && isNonZeroLoadImmediate(*MI))
- return true;
- return false;
+ MachineInstr *MI = MRI.getUniqueVRegDef(getAVLReg());
+ assert(MI);
+ return isNonZeroLoadImmediate(*MI);
}
+ if (hasAVLVLMAX())
+ return true;
+ if (hasAVLIgnored())
+ return false;
return false;
}
@@ -544,6 +557,12 @@ class VSETVLIInfo {
if (hasAVLImm() && Other.hasAVLImm())
return getAVLImm() == Other.getAVLImm();
+ if (hasAVLVLMAX())
+ return Other.hasAVLVLMAX() && hasSameVLMAX(Other);
+
+ if (hasAVLIgnored())
+ return Other.hasAVLIgnored();
+
return false;
}
@@ -717,6 +736,10 @@ class VSETVLIInfo {
OS << "AVLReg=" << (unsigned)AVLReg;
if (hasAVLImm())
OS << "AVLImm=" << (unsigned)AVLImm;
+ if (hasAVLVLMAX())
+ OS << "AVLVLMAX";
+ if (hasAVLIgnored())
+ OS << "AVLIgnored";
OS << ", "
<< "VLMul=" << (unsigned)VLMul << ", "
<< "SEW=" << (unsigned)SEW << ", "
@@ -846,7 +869,10 @@ static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
Register AVLReg = MI.getOperand(1).getReg();
assert((AVLReg != RISCV::X0 || MI.getOperand(0).getReg() != RISCV::X0) &&
"Can't handle X0, X0 vsetvli yet");
- NewInfo.setAVLReg(AVLReg);
+ if (AVLReg == RISCV::X0)
+ NewInfo.setAVLVLMAX();
+ else
+ NewInfo.setAVLReg(AVLReg);
}
NewInfo.setVTYPE(MI.getOperand(2).getImm());
@@ -913,7 +939,7 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
if (ST.getRealMinVLen() == ST.getRealMaxVLen() && VLMAX <= 31)
InstrInfo.setAVLImm(VLMAX);
else
- InstrInfo.setAVLReg(RISCV::X0);
+ InstrInfo.setAVLVLMAX();
}
else
InstrInfo.setAVLImm(Imm);
@@ -922,7 +948,10 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
}
} else {
assert(isScalarExtractInstr(MI));
- InstrInfo.setAVLReg(RISCV::NoRegister);
+ // TODO: If we are more clever about x0,x0 insertion then we should be able
+ // to deduce that the VL is ignored based off of DemandedFields, and remove
+ // the AVLIsIgnored state. Then we can just use an arbitrary immediate AVL.
+ InstrInfo.setAVLIgnored();
}
#ifndef NDEBUG
if (std::optional<unsigned> EEW = getEEWForLoadStore(MI)) {
@@ -935,14 +964,13 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
// AVL operand with the AVL of the defining vsetvli. We avoid general
// register AVLs to avoid extending live ranges without being sure we can
// kill the original source reg entirely.
- if (InstrInfo.hasAVLReg() && InstrInfo.getAVLReg().isVirtual()) {
- MachineInstr *DefMI = MRI->getVRegDef(InstrInfo.getAVLReg());
- if (DefMI && isVectorConfigInstr(*DefMI)) {
+ if (InstrInfo.hasAVLReg()) {
+ MachineInstr *DefMI = MRI->getUniqueVRegDef(InstrInfo.getAVLReg());
+ if (isVectorConfigInstr(*DefMI)) {
VSETVLIInfo DefInstrInfo = getInfoForVSETVLI(*DefMI);
if (DefInstrInfo.hasSameVLMAX(InstrInfo) &&
- (DefInstrInfo.hasAVLImm() || DefInstrInfo.getAVLReg() == RISCV::X0)) {
+ (DefInstrInfo.hasAVLImm() || DefInstrInfo.hasAVLVLMAX()))
InstrInfo.setAVL(DefInstrInfo);
- }
}
}
@@ -976,19 +1004,18 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
// If our AVL is a virtual register, it might be defined by a VSET(I)VLI. If
// it has the same VLMAX we want and the last VL/VTYPE we observed is the
// same, we can use the X0, X0 form.
- if (Info.hasSameVLMAX(PrevInfo) && Info.hasAVLReg() &&
- Info.getAVLReg().isVirtual()) {
- if (MachineInstr *DefMI = MRI->getVRegDef(Info.getAVLReg())) {
- if (isVectorConfigInstr(*DefMI)) {
- VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
- if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) {
- BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
- .addReg(RISCV::X0, RegState::Define | RegState::Dead)
- .addReg(RISCV::X0, RegState::Kill)
- .addImm(Info.encodeVTYPE())
- .addReg(RISCV::VL, RegState::Implicit);
- return;
- }
+ if (Info.hasSameVLMAX(PrevInfo) && Info.hasAVLReg()) {
+ MachineInstr *DefMI = MRI->getUniqueVRegDef(Info.getAVLReg());
+ assert(DefMI);
+ if (isVectorConfigInstr(*DefMI)) {
+ VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
+ if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) {
+ BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
+ .addReg(RISCV::X0, RegState::Define | RegState::Dead)
+ .addReg(RISCV::X0, RegState::Kill)
+ .addImm(Info.encodeVTYPE())
+ .addReg(RISCV::VL, RegState::Implicit);
+ return;
}
}
}
@@ -1002,8 +1029,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
return;
}
- Register AVLReg = Info.getAVLReg();
- if (AVLReg == RISCV::NoRegister) {
+ if (Info.hasAVLIgnored()) {
// We can only use x0, x0 if there's no chance of the vtype change causing
// the previous vl to become invalid.
if (PrevInfo.isValid() && !PrevInfo.isUnknown() &&
@@ -1023,20 +1049,19 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
return;
}
- if (AVLReg.isVirtual())
- MRI->constrainRegClass(AVLReg, &RISCV::GPRNoX0RegClass);
-
- // Use X0 as the DestReg unless AVLReg is X0. We also need to change the
- // opcode if the AVLReg is X0 as they have different register classes for
- // the AVL operand.
- Register DestReg = RISCV::X0;
- unsigned Opcode = RISCV::PseudoVSETVLI;
- if (AVLReg == RISCV::X0) {
- DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
- Opcode = RISCV::PseudoVSETVLIX0;
+ if (Info.hasAVLVLMAX()) {
+ Register DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
+ BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
+ .addReg(DestReg, RegState::Define | RegState::Dead)
+ .addReg(RISCV::X0, RegState::Kill)
+ .addImm(Info.encodeVTYPE());
+ return;
}
- BuildMI(MBB, InsertPt, DL, TII->get(Opcode))
- .addReg(DestReg, RegState::Define | RegState::Dead)
+
+ Register AVLReg = Info.getAVLReg();
+ MRI->constrainRegClass(AVLReg, &RISCV::GPRNoX0RegClass);
+ BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLI))
+ .addReg(RISCV::X0, RegState::Define | RegState::Dead)
.addReg(AVLReg)
.addImm(Info.encodeVTYPE());
}
@@ -1098,14 +1123,13 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
// it might be defined by a VSET(I)VLI. If it has the same VLMAX we need
// and the last VL/VTYPE we observed is the same, we don't need a
// VSETVLI here.
- if (Require.hasAVLReg() && Require.getAVLReg().isVirtual() &&
- CurInfo.hasCompatibleVTYPE(Used, Require)) {
- if (MachineInstr *DefMI = MRI->getVRegDef(Require.getAVLReg())) {
- if (isVectorConfigInstr(*DefMI)) {
- VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
- if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVLMAX(CurInfo))
- return false;
- }
+ if (Require.hasAVLReg() && CurInfo.hasCompatibleVTYPE(Used, Require)) {
+ MachineInstr *DefMI = MRI->getUniqueVRegDef(Require.getAVLReg());
+ assert(DefMI);
+ if (isVectorConfigInstr(*DefMI)) {
+ VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
+ if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVLMAX(CurInfo))
+ return false;
}
}
@@ -1463,10 +1487,9 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
// If the AVL value is a register (other than our VLMAX sentinel),
// we need to prove the value is available at the point we're going
// to insert the vsetvli at.
- if (AvailableInfo.hasAVLReg() && RISCV::X0 != AvailableInfo.getAVLReg()) {
- MachineInstr *AVLDefMI = MRI->getVRegDef(AvailableInfo.getAVLReg());
- if (!AVLDefMI)
- return;
+ if (AvailableInfo.hasAVLReg()) {
+ MachineInstr *AVLDefMI = MRI->getUniqueVRegDef(AvailableInfo.getAVLReg());
+ assert(AVLDefMI);
// This is an inline dominance check which covers the case of
// UnavailablePred being the preheader of a loop.
if (AVLDefMI->getParent() != UnavailablePred)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
index fdcce72a01eb3d..596ea1c39fcea8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
@@ -517,10 +517,10 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
- ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 223 /* e64, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 killed $x0, 223 /* e64, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVID_V_MF2_:%[0-9]+]]:vr = PseudoVID_V_MF2 %pt, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: %pt2:vr = IMPLICIT_DEF
- ; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gpr = PseudoVSETVLIX0 killed $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 %pt2, 0, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -609,7 +609,7 @@ body: |
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
- ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 %pt, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: {{ $}}
@@ -681,7 +681,7 @@ body: |
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
- ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 %pt, -1, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: {{ $}}
@@ -866,7 +866,7 @@ body: |
; CHECK-NEXT: %t3:vr = COPY $v2
; CHECK-NEXT: %t4:vr = COPY $v3
; CHECK-NEXT: %t5:vrnov0 = COPY $v1
- ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %t6:vr = PseudoVMSEQ_VI_M1 %t1, 0, -1, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}}
@@ -949,7 +949,7 @@ body: |
; CHECK-NEXT: %vlenb:gpr = PseudoReadVLENB
; CHECK-NEXT: %inc:gpr = SRLI killed %vlenb, 3
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
- ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 %pt, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: PseudoBR %bb.1
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
index 39f517a100f527..e567897aa86897 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
@@ -324,7 +324,7 @@ body: |
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 %pt, [[COPY]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x)
- ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 $noreg, 0, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
@@ -370,7 +370,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8
- ; CHECK-NEXT: [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: dead [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]
@@ -445,9 +445,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 217 /* e64, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: [[PseudoVID_V_M2_:%[0-9]+]]:vrm2 = PseudoVID_V_M2 %pt, 4, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: dead [[PseudoVID_V_M2_:%[0-9]+]]:vrm2 = PseudoVID_V_M2 %pt, 4, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 198 /* e8, mf4, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
- ; CHECK-NEXT: [[PseudoVMV_V_I_MF4_:%[0-9]+]]:vr = PseudoVMV_V_I_MF4 $noreg, 0, 4, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: dead [[PseudoVMV_V_I_MF4_:%[0-9]+]]:vr = PseudoVMV_V_I_MF4 $noreg, 0, 4, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoRET
%pt:vrm2 = IMPLICIT_DEF
%0:vrm2 = PseudoVID_V_M2 %pt, 4, 6, 3
@@ -467,14 +467,14 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cond:gpr = COPY $x10
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 1, 2, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: dead [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 1, 2, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: BEQ %cond, $x0, %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
- ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 $noreg, 1, 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: dead [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 $noreg, 1, 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)
@@ -488,8 +488,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4:
; CHECK-NEXT: $x0 = PseudoVSETIVLI 2, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S $noreg, 5 /* e32 */, implicit $vtype
- ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_1:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 1, 2, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: dead [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S $noreg, 5 /* e32 */, implicit $vtype
+ ; CHECK-NEXT: dead [[PseudoVMV_V_I_MF2_1:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 1, 2, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoRET
bb.0:
liveins: $x10
@@ -517,10 +517,10 @@ body: |
; CHECK: liveins: $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $vtype
+ ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:gpr = COPY $vtype
; CHECK-NEXT: $vl = COPY $x1
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: dead [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoRET
dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype
%1:gpr = COPY $vtype
>From 671998311c475f3164d569528b50cb3274306220 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 18 Apr 2024 00:30:46 -0700
Subject: [PATCH 2/5] [RISCV] Keep AVLReg define instr inside VSETVLInfo
Currently, the vsetvli pass track the define instruction through MRI->getVRegDef due to the SSA form.
This patch keeps the AVLReg DefMI within VSETVLInfo during construction. And replace MRI->getVRegDef(AVLReg) with getAVLRegDefMI().
This information is useful when vsetvli pass live in post-ra situation.
The testcases don't change because the VReg always has a unique def in SSA.
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 48 ++++++++++++--------
1 file changed, 30 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 1a73e6c5700b85..ddd17a534d84f2 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -156,7 +156,7 @@ static std::optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
}
}
-static bool isNonZeroLoadImmediate(MachineInstr &MI) {
+static bool isNonZeroLoadImmediate(const MachineInstr &MI) {
return MI.getOpcode() == RISCV::ADDI &&
MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
MI.getOperand(1).getReg() == RISCV::X0 &&
@@ -448,6 +448,8 @@ class VSETVLIInfo {
unsigned AVLImm;
};
+ const MachineInstr *AVLDefMI;
+
enum : uint8_t {
Uninitialized,
AVLIsReg,
@@ -466,7 +468,7 @@ class VSETVLIInfo {
public:
VSETVLIInfo()
- : AVLImm(0), TailAgnostic(false), MaskAgnostic(false),
+ : AVLImm(0), AVLDefMI(nullptr), TailAgnostic(false), MaskAgnostic(false),
SEWLMULRatioOnly(false) {}
static VSETVLIInfo getUnknown() {
@@ -493,6 +495,7 @@ class VSETVLIInfo {
void setAVLVLMAX() { State = AVLIsVLMAX; }
void setAVLIgnored() { State = AVLIsIgnored; }
+ void setAVLDefMI(const MachineInstr *DefMI) { AVLDefMI = DefMI; }
bool hasAVLImm() const { return State == AVLIsImm; }
bool hasAVLReg() const { return State == AVLIsReg; }
@@ -507,12 +510,16 @@ class VSETVLIInfo {
return AVLImm;
}
+ const MachineInstr *getAVLDefMI() const { return AVLDefMI; }
+
void setAVL(VSETVLIInfo Info) {
assert(Info.isValid());
if (Info.isUnknown())
setUnknown();
- else if (Info.hasAVLReg())
+ else if (Info.hasAVLReg()) {
setAVLReg(Info.getAVLReg());
+ setAVLDefMI(Info.getAVLDefMI());
+ }
else if (Info.hasAVLVLMAX())
setAVLVLMAX();
else if (Info.hasAVLIgnored())
@@ -532,7 +539,7 @@ class VSETVLIInfo {
if (hasAVLImm())
return getAVLImm() > 0;
if (hasAVLReg()) {
- MachineInstr *MI = MRI.getUniqueVRegDef(getAVLReg());
+ const MachineInstr *MI = getAVLDefMI();
assert(MI);
return isNonZeroLoadImmediate(*MI);
}
@@ -859,7 +866,8 @@ INITIALIZE_PASS(RISCVCoalesceVSETVLI, "riscv-coalesce-vsetvli",
// Return a VSETVLIInfo representing the changes made by this VSETVLI or
// VSETIVLI instruction.
-static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
+static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI,
+ const MachineRegisterInfo &MRI) {
VSETVLIInfo NewInfo;
if (MI.getOpcode() == RISCV::PseudoVSETIVLI) {
NewInfo.setAVLImm(MI.getOperand(1).getImm());
@@ -872,7 +880,7 @@ static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
if (AVLReg == RISCV::X0)
NewInfo.setAVLVLMAX();
else
- NewInfo.setAVLReg(AVLReg);
+ NewInfo.setAVLDefMI(MRI.getVRegDef(AVLReg));
}
NewInfo.setVTYPE(MI.getOperand(2).getImm());
@@ -945,6 +953,8 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
InstrInfo.setAVLImm(Imm);
} else {
InstrInfo.setAVLReg(VLOp.getReg());
+ if (VLOp.getReg().isVirtual())
+ InstrInfo.setAVLDefMI(MRI->getVRegDef(VLOp.getReg()));
}
} else {
assert(isScalarExtractInstr(MI));
@@ -965,9 +975,9 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
// register AVLs to avoid extending live ranges without being sure we can
// kill the original source reg entirely.
if (InstrInfo.hasAVLReg()) {
- MachineInstr *DefMI = MRI->getUniqueVRegDef(InstrInfo.getAVLReg());
- if (isVectorConfigInstr(*DefMI)) {
- VSETVLIInfo DefInstrInfo = getInfoForVSETVLI(*DefMI);
+ const MachineInstr *DefMI = InstrInfo.getAVLDefMI();
+ if (DefMI && isVectorConfigInstr(*DefMI)) {
+ VSETVLIInfo DefInstrInfo = getInfoForVSETVLI(*DefMI, *MRI);
if (DefInstrInfo.hasSameVLMAX(InstrInfo) &&
(DefInstrInfo.hasAVLImm() || DefInstrInfo.hasAVLVLMAX()))
InstrInfo.setAVL(DefInstrInfo);
@@ -1005,10 +1015,10 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
// it has the same VLMAX we want and the last VL/VTYPE we observed is the
// same, we can use the X0, X0 form.
if (Info.hasSameVLMAX(PrevInfo) && Info.hasAVLReg()) {
- MachineInstr *DefMI = MRI->getUniqueVRegDef(Info.getAVLReg());
+ const MachineInstr *DefMI = Info.getAVLDefMI();
assert(DefMI);
if (isVectorConfigInstr(*DefMI)) {
- VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
+ VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI, *MRI);
if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) {
BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
@@ -1126,8 +1136,8 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
if (Require.hasAVLReg() && CurInfo.hasCompatibleVTYPE(Used, Require)) {
MachineInstr *DefMI = MRI->getUniqueVRegDef(Require.getAVLReg());
assert(DefMI);
- if (isVectorConfigInstr(*DefMI)) {
- VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
+ if (Require.getAVLDefMI() && isVectorConfigInstr(*Require.getAVLDefMI())) {
+ VSETVLIInfo DefInfo = getInfoForVSETVLI(*Require.getAVLDefMI(), *MRI);
if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVLMAX(CurInfo))
return false;
}
@@ -1213,13 +1223,15 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
const MachineInstr &MI) const {
if (isVectorConfigInstr(MI)) {
- Info = getInfoForVSETVLI(MI);
+ Info = getInfoForVSETVLI(MI, *MRI);
return;
}
if (RISCV::isFaultFirstLoad(MI)) {
// Update AVL to vl-output of the fault first load.
Info.setAVLReg(MI.getOperand(1).getReg());
+ if (MI.getOperand(1).getReg().isVirtual())
+ Info.setAVLDefMI(MRI->getVRegDef(MI.getOperand(1).getReg()));
return;
}
@@ -1339,7 +1351,7 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
// We found a VSET(I)VLI make sure it matches the output of the
// predecessor block.
- VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
+ VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI, *MRI);
if (!DefInfo.hasSameAVL(PBBInfo.Exit) ||
!DefInfo.hasSameVTYPE(PBBInfo.Exit))
return true;
@@ -1488,7 +1500,7 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
// we need to prove the value is available at the point we're going
// to insert the vsetvli at.
if (AvailableInfo.hasAVLReg()) {
- MachineInstr *AVLDefMI = MRI->getUniqueVRegDef(AvailableInfo.getAVLReg());
+ const MachineInstr *AVLDefMI = AvailableInfo.getAVLDefMI();
assert(AVLDefMI);
// This is an inline dominance check which covers the case of
// UnavailablePred being the preheader of a loop.
@@ -1573,8 +1585,8 @@ static bool canMutatePriorConfig(const MachineInstr &PrevMI,
if (Used.VLZeroness) {
if (isVLPreservingConfig(PrevMI))
return false;
- if (!getInfoForVSETVLI(PrevMI).hasEquallyZeroAVL(getInfoForVSETVLI(MI),
- MRI))
+ if (!getInfoForVSETVLI(PrevMI, MRI)
+ .hasEquallyZeroAVL(getInfoForVSETVLI(MI, MRI), MRI))
return false;
}
>From df3319a546d8c535ffaa854bc546ad6b5c54c55f Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 24 Apr 2024 07:24:12 -0700
Subject: [PATCH 3/5] Get rid of MRI from hasNonZeroAVL and hasEquallyZeroAVL
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index ddd17a534d84f2..c070f0ff7cfe9a 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -535,7 +535,7 @@ class VSETVLIInfo {
bool getTailAgnostic() const { return TailAgnostic; }
bool getMaskAgnostic() const { return MaskAgnostic; }
- bool hasNonZeroAVL(const MachineRegisterInfo &MRI) const {
+ bool hasNonZeroAVL() const {
if (hasAVLImm())
return getAVLImm() > 0;
if (hasAVLReg()) {
@@ -550,11 +550,10 @@ class VSETVLIInfo {
return false;
}
- bool hasEquallyZeroAVL(const VSETVLIInfo &Other,
- const MachineRegisterInfo &MRI) const {
+ bool hasEquallyZeroAVL(const VSETVLIInfo &Other) const {
if (hasSameAVL(Other))
return true;
- return (hasNonZeroAVL(MRI) && Other.hasNonZeroAVL(MRI));
+ return (hasNonZeroAVL() && Other.hasNonZeroAVL());
}
bool hasSameAVL(const VSETVLIInfo &Other) const {
@@ -655,7 +654,7 @@ class VSETVLIInfo {
if (Used.VLAny && !(hasSameAVL(Require) && hasSameVLMAX(Require)))
return false;
- if (Used.VLZeroness && !hasEquallyZeroAVL(Require, MRI))
+ if (Used.VLZeroness && !hasEquallyZeroAVL(Require))
return false;
return hasCompatibleVTYPE(Used, Require);
@@ -1192,7 +1191,7 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
// variant, so we avoid the transform to prevent extending live range of an
// avl register operand.
// TODO: We can probably relax this for immediates.
- bool EquallyZero = IncomingInfo.hasEquallyZeroAVL(PrevInfo, *MRI) &&
+ bool EquallyZero = IncomingInfo.hasEquallyZeroAVL(PrevInfo) &&
IncomingInfo.hasSameVLMAX(PrevInfo);
if (Demanded.VLAny || (Demanded.VLZeroness && !EquallyZero))
Info.setAVL(IncomingInfo);
@@ -1586,7 +1585,7 @@ static bool canMutatePriorConfig(const MachineInstr &PrevMI,
if (isVLPreservingConfig(PrevMI))
return false;
if (!getInfoForVSETVLI(PrevMI, MRI)
- .hasEquallyZeroAVL(getInfoForVSETVLI(MI, MRI), MRI))
+ .hasEquallyZeroAVL(getInfoForVSETVLI(MI, MRI)))
return false;
}
>From 2dc09aa5b64e07318bb9161b943ff2e06be46009 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 24 Apr 2024 21:29:41 -0700
Subject: [PATCH 4/5] Merge setDefMI into setReg
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 30 ++++++++++----------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index c070f0ff7cfe9a..bdd9f082278b87 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -452,7 +452,7 @@ class VSETVLIInfo {
enum : uint8_t {
Uninitialized,
- AVLIsReg,
+ AVLIsDefMI,
AVLIsImm,
AVLIsVLMAX,
AVLIsIgnored,
@@ -481,10 +481,11 @@ class VSETVLIInfo {
void setUnknown() { State = Unknown; }
bool isUnknown() const { return State == Unknown; }
- void setAVLReg(Register Reg) {
+ void setAVLReg(Register Reg, const MachineInstr *DefMI) {
assert(Reg.isVirtual());
AVLReg = Reg;
- State = AVLIsReg;
+ AVLDefMI = DefMI;
+ State = AVLIsDefMI;
}
void setAVLImm(unsigned Imm) {
@@ -498,7 +499,7 @@ class VSETVLIInfo {
void setAVLDefMI(const MachineInstr *DefMI) { AVLDefMI = DefMI; }
bool hasAVLImm() const { return State == AVLIsImm; }
- bool hasAVLReg() const { return State == AVLIsReg; }
+ bool hasAVLReg() const { return State == AVLIsDefMI; }
bool hasAVLVLMAX() const { return State == AVLIsVLMAX; }
bool hasAVLIgnored() const { return State == AVLIsIgnored; }
Register getAVLReg() const {
@@ -516,10 +517,8 @@ class VSETVLIInfo {
assert(Info.isValid());
if (Info.isUnknown())
setUnknown();
- else if (Info.hasAVLReg()) {
- setAVLReg(Info.getAVLReg());
- setAVLDefMI(Info.getAVLDefMI());
- }
+ else if (Info.hasAVLReg())
+ setAVLReg(Info.getAVLReg(), Info.getAVLDefMI());
else if (Info.hasAVLVLMAX())
setAVLVLMAX();
else if (Info.hasAVLIgnored())
@@ -879,7 +878,7 @@ static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI,
if (AVLReg == RISCV::X0)
NewInfo.setAVLVLMAX();
else
- NewInfo.setAVLDefMI(MRI.getVRegDef(AVLReg));
+ NewInfo.setAVLReg(AVLReg, MRI.getVRegDef(AVLReg));
}
NewInfo.setVTYPE(MI.getOperand(2).getImm());
@@ -951,9 +950,9 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
else
InstrInfo.setAVLImm(Imm);
} else {
- InstrInfo.setAVLReg(VLOp.getReg());
- if (VLOp.getReg().isVirtual())
- InstrInfo.setAVLDefMI(MRI->getVRegDef(VLOp.getReg()));
+ InstrInfo.setAVLReg(VLOp.getReg(), VLOp.getReg().isVirtual()
+ ? MRI->getVRegDef(VLOp.getReg())
+ : nullptr);
}
} else {
assert(isScalarExtractInstr(MI));
@@ -1228,9 +1227,10 @@ void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
if (RISCV::isFaultFirstLoad(MI)) {
// Update AVL to vl-output of the fault first load.
- Info.setAVLReg(MI.getOperand(1).getReg());
- if (MI.getOperand(1).getReg().isVirtual())
- Info.setAVLDefMI(MRI->getVRegDef(MI.getOperand(1).getReg()));
+ Info.setAVLReg(MI.getOperand(1).getReg(),
+ MI.getOperand(1).getReg().isVirtual()
+ ? MRI->getVRegDef(MI.getOperand(1).getReg())
+ : nullptr);
return;
}
>From efc895c284a2a34a92ebca884468f4c8c38c48bb Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 24 Apr 2024 23:08:35 -0700
Subject: [PATCH 5/5] Replace the setAVLReg and AVLIsReg with DefMI
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 70 +++++++++-----------
1 file changed, 30 insertions(+), 40 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index bdd9f082278b87..def3cbace9afab 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -444,12 +444,10 @@ DemandedFields getDemanded(const MachineInstr &MI,
/// values of the VL and VTYPE registers after insertion.
class VSETVLIInfo {
union {
- Register AVLReg;
+ const MachineInstr *AVLDefMI;
unsigned AVLImm;
};
- const MachineInstr *AVLDefMI;
-
enum : uint8_t {
Uninitialized,
AVLIsDefMI,
@@ -468,7 +466,7 @@ class VSETVLIInfo {
public:
VSETVLIInfo()
- : AVLImm(0), AVLDefMI(nullptr), TailAgnostic(false), MaskAgnostic(false),
+ : AVLImm(0), TailAgnostic(false), MaskAgnostic(false),
SEWLMULRatioOnly(false) {}
static VSETVLIInfo getUnknown() {
@@ -481,9 +479,8 @@ class VSETVLIInfo {
void setUnknown() { State = Unknown; }
bool isUnknown() const { return State == Unknown; }
- void setAVLReg(Register Reg, const MachineInstr *DefMI) {
- assert(Reg.isVirtual());
- AVLReg = Reg;
+ void setAVLDefMI(const MachineInstr *DefMI) {
+ assert(DefMI);
AVLDefMI = DefMI;
State = AVLIsDefMI;
}
@@ -496,29 +493,31 @@ class VSETVLIInfo {
void setAVLVLMAX() { State = AVLIsVLMAX; }
void setAVLIgnored() { State = AVLIsIgnored; }
- void setAVLDefMI(const MachineInstr *DefMI) { AVLDefMI = DefMI; }
bool hasAVLImm() const { return State == AVLIsImm; }
- bool hasAVLReg() const { return State == AVLIsDefMI; }
+ bool hasAVLDefMI() const { return State == AVLIsDefMI; }
bool hasAVLVLMAX() const { return State == AVLIsVLMAX; }
bool hasAVLIgnored() const { return State == AVLIsIgnored; }
Register getAVLReg() const {
- assert(hasAVLReg());
- return AVLReg;
+ assert(hasAVLDefMI());
+ return AVLDefMI->getOperand(0).getReg();
}
unsigned getAVLImm() const {
assert(hasAVLImm());
return AVLImm;
}
- const MachineInstr *getAVLDefMI() const { return AVLDefMI; }
+ const MachineInstr *getAVLDefMI() const {
+ assert(AVLDefMI);
+ return AVLDefMI;
+ }
void setAVL(VSETVLIInfo Info) {
assert(Info.isValid());
if (Info.isUnknown())
setUnknown();
- else if (Info.hasAVLReg())
- setAVLReg(Info.getAVLReg(), Info.getAVLDefMI());
+ else if (Info.hasAVLDefMI())
+ setAVLDefMI(Info.getAVLDefMI());
else if (Info.hasAVLVLMAX())
setAVLVLMAX();
else if (Info.hasAVLIgnored())
@@ -537,7 +536,7 @@ class VSETVLIInfo {
bool hasNonZeroAVL() const {
if (hasAVLImm())
return getAVLImm() > 0;
- if (hasAVLReg()) {
+ if (hasAVLDefMI()) {
const MachineInstr *MI = getAVLDefMI();
assert(MI);
return isNonZeroLoadImmediate(*MI);
@@ -556,8 +555,8 @@ class VSETVLIInfo {
}
bool hasSameAVL(const VSETVLIInfo &Other) const {
- if (hasAVLReg() && Other.hasAVLReg())
- return getAVLReg() == Other.getAVLReg();
+ if (hasAVLDefMI() && Other.hasAVLDefMI())
+ return getAVLDefMI()->isIdenticalTo(*Other.getAVLDefMI());
if (hasAVLImm() && Other.hasAVLImm())
return getAVLImm() == Other.getAVLImm();
@@ -737,8 +736,8 @@ class VSETVLIInfo {
OS << "Uninitialized";
if (isUnknown())
OS << "unknown";
- if (hasAVLReg())
- OS << "AVLReg=" << (unsigned)AVLReg;
+ if (hasAVLDefMI())
+ OS << "AVLReg=" << (unsigned)getAVLReg();
if (hasAVLImm())
OS << "AVLImm=" << (unsigned)AVLImm;
if (hasAVLVLMAX())
@@ -878,7 +877,7 @@ static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI,
if (AVLReg == RISCV::X0)
NewInfo.setAVLVLMAX();
else
- NewInfo.setAVLReg(AVLReg, MRI.getVRegDef(AVLReg));
+ NewInfo.setAVLDefMI(MRI.getVRegDef(AVLReg));
}
NewInfo.setVTYPE(MI.getOperand(2).getImm());
@@ -950,9 +949,7 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
else
InstrInfo.setAVLImm(Imm);
} else {
- InstrInfo.setAVLReg(VLOp.getReg(), VLOp.getReg().isVirtual()
- ? MRI->getVRegDef(VLOp.getReg())
- : nullptr);
+ InstrInfo.setAVLDefMI(MRI->getVRegDef(VLOp.getReg()));
}
} else {
assert(isScalarExtractInstr(MI));
@@ -972,7 +969,7 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
// AVL operand with the AVL of the defining vsetvli. We avoid general
// register AVLs to avoid extending live ranges without being sure we can
// kill the original source reg entirely.
- if (InstrInfo.hasAVLReg()) {
+ if (InstrInfo.hasAVLDefMI()) {
const MachineInstr *DefMI = InstrInfo.getAVLDefMI();
if (DefMI && isVectorConfigInstr(*DefMI)) {
VSETVLIInfo DefInstrInfo = getInfoForVSETVLI(*DefMI, *MRI);
@@ -1012,7 +1009,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
// If our AVL is a virtual register, it might be defined by a VSET(I)VLI. If
// it has the same VLMAX we want and the last VL/VTYPE we observed is the
// same, we can use the X0, X0 form.
- if (Info.hasSameVLMAX(PrevInfo) && Info.hasAVLReg()) {
+ if (Info.hasSameVLMAX(PrevInfo) && Info.hasAVLDefMI()) {
const MachineInstr *DefMI = Info.getAVLDefMI();
assert(DefMI);
if (isVectorConfigInstr(*DefMI)) {
@@ -1131,11 +1128,11 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
// it might be defined by a VSET(I)VLI. If it has the same VLMAX we need
// and the last VL/VTYPE we observed is the same, we don't need a
// VSETVLI here.
- if (Require.hasAVLReg() && CurInfo.hasCompatibleVTYPE(Used, Require)) {
- MachineInstr *DefMI = MRI->getUniqueVRegDef(Require.getAVLReg());
+ if (Require.hasAVLDefMI() && CurInfo.hasCompatibleVTYPE(Used, Require)) {
+ const MachineInstr *DefMI = Require.getAVLDefMI();
assert(DefMI);
- if (Require.getAVLDefMI() && isVectorConfigInstr(*Require.getAVLDefMI())) {
- VSETVLIInfo DefInfo = getInfoForVSETVLI(*Require.getAVLDefMI(), *MRI);
+ if (DefMI && isVectorConfigInstr(*DefMI)) {
+ VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI, *MRI);
if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVLMAX(CurInfo))
return false;
}
@@ -1227,10 +1224,7 @@ void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
if (RISCV::isFaultFirstLoad(MI)) {
// Update AVL to vl-output of the fault first load.
- Info.setAVLReg(MI.getOperand(1).getReg(),
- MI.getOperand(1).getReg().isVirtual()
- ? MRI->getVRegDef(MI.getOperand(1).getReg())
- : nullptr);
+ Info.setAVLDefMI(MRI->getVRegDef(MI.getOperand(1).getReg()));
return;
}
@@ -1321,15 +1315,11 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
if (DisableInsertVSETVLPHIOpt)
return true;
- if (!Require.hasAVLReg())
- return true;
-
- Register AVLReg = Require.getAVLReg();
- if (!AVLReg.isVirtual())
+ if (!Require.hasAVLDefMI())
return true;
// We need the AVL to be produce by a PHI node in this basic block.
- MachineInstr *PHI = MRI->getVRegDef(AVLReg);
+ const MachineInstr *PHI = Require.getAVLDefMI();
if (!PHI || PHI->getOpcode() != RISCV::PHI || PHI->getParent() != &MBB)
return true;
@@ -1498,7 +1488,7 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
// If the AVL value is a register (other than our VLMAX sentinel),
// we need to prove the value is available at the point we're going
// to insert the vsetvli at.
- if (AvailableInfo.hasAVLReg()) {
+ if (AvailableInfo.hasAVLDefMI()) {
const MachineInstr *AVLDefMI = AvailableInfo.getAVLDefMI();
assert(AVLDefMI);
// This is an inline dominance check which covers the case of
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