[llvm] [RISCV] Re-model RVV comparison instructions (PR #88868)

[Luke Lau via llvm-commits]

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@@ -88,11 +88,11 @@ define <vscale x 16 x i1> @nxv16i1(i1 %x, i1 %y) {
 ; CHECK-NEXT:    andi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a2, zero, e8, m2, ta, ma
 ; CHECK-NEXT:    vmv.v.x v8, a0
-; CHECK-NEXT:    vmsne.vi v10, v8, 0
+; CHECK-NEXT:    vmsne.vi v0, v8, 0
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lukel97 wrote:

I was thinking that `MachineRegisterInfo::recomputeRegClass` might be able to change a VMM8 register to VR. But after reading the function, I don't think it will if the compare instruction is still around since that will still have the constraint. 

So I presume we'll end up with spilling if we have more than four LMUL8 compare results live at the same time? It would be good to know how often that happens in practice

https://github.com/llvm/llvm-project/pull/88868