[llvm] [RISCV] Defer forming x0, x0 vsetvlis until after insertion (PR #89089)

[Luke Lau via llvm-commits]

lukel97 wrote:

Marking as a draft as I can't think of an easy way to rebase this after #88295, as it requires using dataflow analysis after register coalescing which is now in a separate pass. Will revisit once #70549 lands

https://github.com/llvm/llvm-project/pull/89089