[llvm] [AMDGPU] Set glc bit for nontemporal loads on GFX10/11 (PR #89739)
Fabian Ritter via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 23 04:28:28 PDT 2024
https://github.com/ritter-x2a created https://github.com/llvm/llvm-project/pull/89739
With glc and slc set, nontemporal loads go to the L2 cache while matching entries from L0 and L1 are evicted.
Without glc set (the state prior to this patch), nontemporal loads would read from the L0 cache and affect its cache state.
See section 8.1.10 in the RDNA 1 and 2 ISA reference [1,2] for gfx10 and section 4.1.1 in the RDNA 3 ISA reference [3] for gfx11.
Fixes SWDEV-456064
---
[1] https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna-shader-instruction-set-architecture.pdf
[2] https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna2-shader-instruction-set-architecture.pdf
[3] https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna3-shader-instruction-set-architecture-feb-2023_0.pdf
>From 5f1f2bb0a940a85a0cba72edb2524fbc6a5c0e59 Mon Sep 17 00:00:00 2001
From: Fabian Ritter <fabian.ritter at amd.com>
Date: Mon, 22 Apr 2024 06:59:41 -0400
Subject: [PATCH] [AMDGPU] Set glc bit for nontemporal loads on GFX10/11
With glc and slc set, nontemporal loads go to the L2 cache while
matching entries from L0 and L1 are evicted.
Without glc set (the state prior to this patch), nontemporal loads would
read from the L0 cache and affect its cache state.
See section 8.1.10 in the RDNA 1 and 2 ISA reference [1,2] for gfx10 and
section 4.1.1 in the RDNA 3 ISA reference [3] for gfx11.
Fixes SWDEV-456064
---
[1] https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna-shader-instruction-set-architecture.pdf
[2] https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna2-shader-instruction-set-architecture.pdf
[3] https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna3-shader-instruction-set-architecture-feb-2023_0.pdf
---
llvm/docs/AMDGPUUsage.rst | 2 +-
llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp | 18 ++++++------------
.../memory-legalizer-flat-nontemporal.ll | 16 ++++++++--------
.../memory-legalizer-global-nontemporal.ll | 8 ++++----
.../memory-legalizer-private-nontemporal.ll | 16 ++++++++--------
5 files changed, 27 insertions(+), 33 deletions(-)
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 029db00134c09d..428aa02fd23641 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -12192,7 +12192,7 @@ table :ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx10-gfx11-table`.
- !volatile & nontemporal
1. buffer/global/flat_load
- slc=1 dlc=1
+ glc=1 slc=1 dlc=1
- If GFX10, omit dlc=1.
diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
index 62306fa667b360..16989a01162b6f 100644
--- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
@@ -1898,12 +1898,9 @@ bool SIGfx10CacheControl::enableVolatileAndOrNonTemporal(
}
if (IsNonTemporal) {
- // For loads setting SLC configures L0 and L1 cache policy to HIT_EVICT
- // and L2 cache policy to STREAM.
- // For stores setting both GLC and SLC configures L0 and L1 cache policy
- // to MISS_EVICT and the L2 cache policy to STREAM.
- if (Op == SIMemOp::STORE)
- Changed |= enableGLCBit(MI);
+ // Setting both GLC and SLC configures L0 and L1 cache policy to MISS_EVICT
+ // and the L2 cache policy to STREAM for loads and stores.
+ Changed |= enableGLCBit(MI);
Changed |= enableSLCBit(MI);
return Changed;
@@ -2170,12 +2167,9 @@ bool SIGfx11CacheControl::enableVolatileAndOrNonTemporal(
}
if (IsNonTemporal) {
- // For loads setting SLC configures L0 and L1 cache policy to HIT_EVICT
- // and L2 cache policy to STREAM.
- // For stores setting both GLC and SLC configures L0 and L1 cache policy
- // to MISS_EVICT and the L2 cache policy to STREAM.
- if (Op == SIMemOp::STORE)
- Changed |= enableGLCBit(MI);
+ // Setting both GLC and SLC configures L0 and L1 cache policy to MISS_EVICT
+ // and the L2 cache policy to STREAM for loads and stores.
+ Changed |= enableGLCBit(MI);
Changed |= enableSLCBit(MI);
// Set MALL NOALLOC for load and store instructions.
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
index f6fac11d634c5b..ecd14d3c108573 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
@@ -32,7 +32,7 @@ define amdgpu_kernel void @flat_nontemporal_load_0(
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
-; GFX10-WGP-NEXT: flat_load_dword v2, v[0:1] slc
+; GFX10-WGP-NEXT: flat_load_dword v2, v[0:1] glc slc
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s3
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -45,7 +45,7 @@ define amdgpu_kernel void @flat_nontemporal_load_0(
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
-; GFX10-CU-NEXT: flat_load_dword v2, v[0:1] slc
+; GFX10-CU-NEXT: flat_load_dword v2, v[0:1] glc slc
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s3
; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -122,7 +122,7 @@ define amdgpu_kernel void @flat_nontemporal_load_0(
; GFX11-WGP-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX11-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-WGP-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-WGP-NEXT: flat_load_b32 v2, v[0:1] slc dlc
+; GFX11-WGP-NEXT: flat_load_b32 v2, v[0:1] glc slc dlc
; GFX11-WGP-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX11-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-WGP-NEXT: flat_store_b32 v[0:1], v2
@@ -133,7 +133,7 @@ define amdgpu_kernel void @flat_nontemporal_load_0(
; GFX11-CU-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-CU-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-CU-NEXT: flat_load_b32 v2, v[0:1] slc dlc
+; GFX11-CU-NEXT: flat_load_b32 v2, v[0:1] glc slc dlc
; GFX11-CU-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2
@@ -190,7 +190,7 @@ define amdgpu_kernel void @flat_nontemporal_load_1(
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_add_co_u32 v0, s0, s0, v0
; GFX10-WGP-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0
-; GFX10-WGP-NEXT: flat_load_dword v2, v[0:1] slc
+; GFX10-WGP-NEXT: flat_load_dword v2, v[0:1] glc slc
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s3
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -204,7 +204,7 @@ define amdgpu_kernel void @flat_nontemporal_load_1(
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_add_co_u32 v0, s0, s0, v0
; GFX10-CU-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0
-; GFX10-CU-NEXT: flat_load_dword v2, v[0:1] slc
+; GFX10-CU-NEXT: flat_load_dword v2, v[0:1] glc slc
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s3
; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -292,7 +292,7 @@ define amdgpu_kernel void @flat_nontemporal_load_1(
; GFX11-WGP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-WGP-NEXT: v_add_co_u32 v0, s0, s0, v0
; GFX11-WGP-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0
-; GFX11-WGP-NEXT: flat_load_b32 v2, v[0:1] slc dlc
+; GFX11-WGP-NEXT: flat_load_b32 v2, v[0:1] glc slc dlc
; GFX11-WGP-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v0, s2
; GFX11-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-WGP-NEXT: flat_store_b32 v[0:1], v2
@@ -306,7 +306,7 @@ define amdgpu_kernel void @flat_nontemporal_load_1(
; GFX11-CU-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-CU-NEXT: v_add_co_u32 v0, s0, s0, v0
; GFX11-CU-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0
-; GFX11-CU-NEXT: flat_load_b32 v2, v[0:1] slc dlc
+; GFX11-CU-NEXT: flat_load_b32 v2, v[0:1] glc slc dlc
; GFX11-CU-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v0, s2
; GFX11-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX11-CU-NEXT: flat_store_b32 v[0:1], v2
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
index c95ff2c691a3cb..bedd7205809908 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
@@ -213,7 +213,7 @@ define amdgpu_kernel void @global_nontemporal_load_1(
; GFX10-WGP-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-WGP-NEXT: global_load_dword v0, v0, s[0:1] slc
+; GFX10-WGP-NEXT: global_load_dword v0, v0, s[0:1] glc slc
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0)
; GFX10-WGP-NEXT: global_store_dword v1, v0, s[2:3]
; GFX10-WGP-NEXT: s_endpgm
@@ -224,7 +224,7 @@ define amdgpu_kernel void @global_nontemporal_load_1(
; GFX10-CU-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-CU-NEXT: global_load_dword v0, v0, s[0:1] slc
+; GFX10-CU-NEXT: global_load_dword v0, v0, s[0:1] glc slc
; GFX10-CU-NEXT: s_waitcnt vmcnt(0)
; GFX10-CU-NEXT: global_store_dword v1, v0, s[2:3]
; GFX10-CU-NEXT: s_endpgm
@@ -295,7 +295,7 @@ define amdgpu_kernel void @global_nontemporal_load_1(
; GFX11-WGP-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX11-WGP-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
; GFX11-WGP-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-WGP-NEXT: global_load_b32 v0, v0, s[0:1] slc dlc
+; GFX11-WGP-NEXT: global_load_b32 v0, v0, s[0:1] glc slc dlc
; GFX11-WGP-NEXT: s_waitcnt vmcnt(0)
; GFX11-WGP-NEXT: global_store_b32 v1, v0, s[2:3]
; GFX11-WGP-NEXT: s_nop 0
@@ -307,7 +307,7 @@ define amdgpu_kernel void @global_nontemporal_load_1(
; GFX11-CU-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX11-CU-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-CU-NEXT: global_load_b32 v0, v0, s[0:1] slc dlc
+; GFX11-CU-NEXT: global_load_b32 v0, v0, s[0:1] glc slc dlc
; GFX11-CU-NEXT: s_waitcnt vmcnt(0)
; GFX11-CU-NEXT: global_store_b32 v1, v0, s[2:3]
; GFX11-CU-NEXT: s_nop 0
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
index 30296a9c3d8963..516dda40ac6d12 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
@@ -60,7 +60,7 @@ define amdgpu_kernel void @private_nontemporal_load_0(
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s2
-; GFX10-WGP-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen slc
+; GFX10-WGP-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc slc
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0)
; GFX10-WGP-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-WGP-NEXT: s_endpgm
@@ -77,7 +77,7 @@ define amdgpu_kernel void @private_nontemporal_load_0(
; GFX10-CU-NEXT: v_mov_b32_e32 v1, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s2
-; GFX10-CU-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen slc
+; GFX10-CU-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc slc
; GFX10-CU-NEXT: s_waitcnt vmcnt(0)
; GFX10-CU-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-CU-NEXT: s_endpgm
@@ -161,7 +161,7 @@ define amdgpu_kernel void @private_nontemporal_load_0(
; GFX11-WGP-NEXT: s_load_b64 s[0:1], s[0:1], 0x8
; GFX11-WGP-NEXT: v_mov_b32_e32 v1, 0
; GFX11-WGP-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-WGP-NEXT: scratch_load_b32 v0, off, s2 slc dlc
+; GFX11-WGP-NEXT: scratch_load_b32 v0, off, s2 glc slc dlc
; GFX11-WGP-NEXT: s_waitcnt vmcnt(0)
; GFX11-WGP-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-WGP-NEXT: s_nop 0
@@ -175,7 +175,7 @@ define amdgpu_kernel void @private_nontemporal_load_0(
; GFX11-CU-NEXT: s_load_b64 s[0:1], s[0:1], 0x8
; GFX11-CU-NEXT: v_mov_b32_e32 v1, 0
; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-CU-NEXT: scratch_load_b32 v0, off, s2 slc dlc
+; GFX11-CU-NEXT: scratch_load_b32 v0, off, s2 glc slc dlc
; GFX11-CU-NEXT: s_waitcnt vmcnt(0)
; GFX11-CU-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-CU-NEXT: s_nop 0
@@ -265,7 +265,7 @@ define amdgpu_kernel void @private_nontemporal_load_1(
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_lshl_add_u32 v0, v0, 2, s2
-; GFX10-WGP-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen slc
+; GFX10-WGP-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc slc
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0)
; GFX10-WGP-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-WGP-NEXT: s_endpgm
@@ -282,7 +282,7 @@ define amdgpu_kernel void @private_nontemporal_load_1(
; GFX10-CU-NEXT: v_mov_b32_e32 v1, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_lshl_add_u32 v0, v0, 2, s2
-; GFX10-CU-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen slc
+; GFX10-CU-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc slc
; GFX10-CU-NEXT: s_waitcnt vmcnt(0)
; GFX10-CU-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-CU-NEXT: s_endpgm
@@ -370,7 +370,7 @@ define amdgpu_kernel void @private_nontemporal_load_1(
; GFX11-WGP-NEXT: v_mov_b32_e32 v1, 0
; GFX11-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-WGP-NEXT: v_lshl_add_u32 v0, v0, 2, s2
-; GFX11-WGP-NEXT: scratch_load_b32 v0, v0, off slc dlc
+; GFX11-WGP-NEXT: scratch_load_b32 v0, v0, off glc slc dlc
; GFX11-WGP-NEXT: s_waitcnt vmcnt(0)
; GFX11-WGP-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-WGP-NEXT: s_nop 0
@@ -385,7 +385,7 @@ define amdgpu_kernel void @private_nontemporal_load_1(
; GFX11-CU-NEXT: v_mov_b32_e32 v1, 0
; GFX11-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-CU-NEXT: v_lshl_add_u32 v0, v0, 2, s2
-; GFX11-CU-NEXT: scratch_load_b32 v0, v0, off slc dlc
+; GFX11-CU-NEXT: scratch_load_b32 v0, v0, off glc slc dlc
; GFX11-CU-NEXT: s_waitcnt vmcnt(0)
; GFX11-CU-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-CU-NEXT: s_nop 0
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