[llvm] [RISCV][ISel] Eliminate `andi rd, rs1, -1` instructions (PR #89976)

[Craig Topper via llvm-commits]

topperc wrote:

Some of these look they would have been caught in DAGCombiner if we implement https://github.com/llvm/llvm-project/issues/56645

https://github.com/llvm/llvm-project/pull/89976