[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Piyou Chen via llvm-commits]

BeMg wrote:

Update with https://github.com/llvm/llvm-project/pull/88295 and https://github.com/llvm/llvm-project/pull/89180.

Based on the previous changes, we must assume that for every AVLReg, there exists a corresponding DefMI. In the non-SSA program, PHI nodes are eliminated, which allows an AVLReg to have more than one DefMI alive in different BasicBlocks.

I add one more DefMI check function to skip the case that can't decide the DefMI.

https://github.com/llvm/llvm-project/pull/70549