[llvm] [RISCV][GlobalISel] Fix selectShiftMask when shift mask is created from G_AND (PR #89602)

[Michael Maitland via llvm-commits]

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@@ -177,14 +177,28 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const {
 
   APInt AndMask;
   Register AndSrcReg;
+  // Try to combine the following pattern (applicable to other shift
+  // instructions as well as 32-bit ones):
+  //
+  //   %4:gprb(s64) = G_AND %3, %2
+  //   %5:gprb(s64) = G_LSHR %1, %4(s64)
+  //
+  // According to RISC-V's ISA manual, SLL, SRL, and SRA ignore other bits than
+  // the lowest log2(XLEN) bits of register rs2. As for the above pattern, if
+  // the lowest bits of register rd and rs2 of G_AND are the same, then it can
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michaelmaitland wrote:

`the lowest bits` -> `the lowest log2(XLEN) bits`

https://github.com/llvm/llvm-project/pull/89602