The Week Of Monday 17 March 2025 Archives by date
Starting: Mon Mar 17 00:01:24 PDT 2025
Ending: Sun Mar 23 23:58:46 PDT 2025
Messages: 5723
- [llvm] [CodeGen] commuteInstruction should update implicit-def (PR #131361)
Matt Arsenault via llvm-commits
- [llvm] [CodeGen] commuteInstruction should update implicit-def (PR #131361)
Matt Arsenault via llvm-commits
- [llvm] [CodeGen] commuteInstruction should update implicit-def (PR #131361)
Matt Arsenault via llvm-commits
- [llvm] [CodeGen] commuteInstruction should update implicit-def (PR #131361)
Matt Arsenault via llvm-commits
- [llvm] [CodeGen][NPM] Port MachineBlockPlacementStats to NPM (PR #129853)
Matt Arsenault via llvm-commits
- [llvm] [AArch64][GlobalISel] Legalize more CTPOP vector types. (PR #131513)
Matt Arsenault via llvm-commits
- [llvm] [AArch64][GlobalISel] Legalize more CTPOP vector types. (PR #131513)
Matt Arsenault via llvm-commits
- [llvm] c3f6d2c - [gn build] Port 3b1e18c2dba8
LLVM GN Syncbot via llvm-commits
- [llvm] [AMDGPU] Add intrinsic and MI for image_bvh_dual_intersect_ray (PR #130038)
Matt Arsenault via llvm-commits
- [llvm] [AMDGPU] Add intrinsic and MI for image_bvh_dual_intersect_ray (PR #130038)
Matt Arsenault via llvm-commits
- [llvm] [AMDGPU] frame index elimination hit assertion for scavenged nonreg (PR #130287)
Pankaj Dwivedi via llvm-commits
- [llvm] 9b1ce47 - [gn build] Port 57e36419b251
LLVM GN Syncbot via llvm-commits
- [clang] [llvm] [RISCV] Add Qualcomm uC Xqcibi (Branch Immediate) extension (PR #130779)
via llvm-commits
- [llvm] [AMDGPU] Hoist readlane/readfirst through unary/binary operands (PR #129037)
Matt Arsenault via llvm-commits
- [llvm] [X86][NFC] Add missing immediate qualifier to VSM3RNDS2 instruction (PR #131576)
Phoebe Wang via llvm-commits
- [llvm] [X86][NFC] Add missing immediate qualifier to VSM3RNDS2 instruction (PR #131576)
via llvm-commits
- [llvm] [SPIRV]Added support for the extension SPV_INTEL_blocking_pipes (PR #131577)
Aadesh PremKumar via llvm-commits
- [llvm] [SPIRV]Added support for the extension SPV_INTEL_blocking_pipes (PR #131577)
via llvm-commits
- [llvm] [SPIRV]Added support for the extension SPV_INTEL_blocking_pipes (PR #131577)
via llvm-commits
- [llvm] [MachineVerifier] Fix LiveInterval verification of unwinding instructions (PR #131565)
Heejin Ahn via llvm-commits
- [clang] [llvm] Define LLVM_ABI and CLANG_ABI for __EMSCRIPTEN__ builds (PR #131578)
Anutosh Bhat via llvm-commits
- [clang] [llvm] Define LLVM_ABI and CLANG_ABI for __EMSCRIPTEN__ builds (PR #131578)
Anutosh Bhat via llvm-commits
- [clang] [llvm] Define LLVM_ABI and CLANG_ABI for __EMSCRIPTEN__ builds (PR #131578)
via llvm-commits
- [clang] [llvm] Define LLVM_ABI and CLANG_ABI for __EMSCRIPTEN__ builds (PR #131578)
via llvm-commits
- [clang] [llvm] Define LLVM_ABI and CLANG_ABI for __EMSCRIPTEN__ builds (PR #131578)
Anutosh Bhat via llvm-commits
- [clang] [llvm] Define LLVM_ABI and CLANG_ABI for __EMSCRIPTEN__ builds (PR #131578)
Anutosh Bhat via llvm-commits
- [clang] [llvm] Define LLVM_ABI and CLANG_ABI for __EMSCRIPTEN__ builds (PR #131578)
Anutosh Bhat via llvm-commits
- [llvm] 6b47bba - [AMDGPU] Add intrinsics and MIs for ds_bvh_stack_* (#130007)
via llvm-commits
- [llvm] [AMDGPU] Add intrinsics and MIs for ds_bvh_stack_* (PR #130007)
Mariusz Sikora via llvm-commits
- [llvm] [AMDGPU][NPM] Support -regalloc-npm options (PR #129035)
Christudasan Devadasan via llvm-commits
- [llvm] [AMDGPU][True16][CodeGen] enable true16 for more codegen test patch 1 (PR #131206)
Mikael Holmén via llvm-commits
- [clang] [llvm] Define LLVM_ABI and CLANG_ABI for __EMSCRIPTEN__ builds (PR #131578)
via llvm-commits
- [llvm] GlobalISel: neg (and x, 1) --> SIGN_EXTEND_INREG x, 1 (PR #131367)
Pierre van Houtryve via llvm-commits
- [llvm] [Exegesis] CPU selection, when native arch and target mismatch (PR #131014)
via llvm-commits
- [llvm] [Exegesis] CPU selection, when native arch and target mismatch (PR #131014)
via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Pierre van Houtryve via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Pierre van Houtryve via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Pierre van Houtryve via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Pierre van Houtryve via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Pierre van Houtryve via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Pierre van Houtryve via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU] frame index elimination hit assertion for scavenged nonreg (PR #130287)
Matt Arsenault via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Matt Arsenault via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Matt Arsenault via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Matt Arsenault via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Matt Arsenault via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Matt Arsenault via llvm-commits
- [llvm] [VPlan] Support early-exit loops in optimizeForVFAndUF. (PR #131539)
David Sherwood via llvm-commits
- [llvm] [VPlan] Support early-exit loops in optimizeForVFAndUF. (PR #131539)
David Sherwood via llvm-commits
- [llvm] [llvm-exegesis] Add myself as an llvm-exegesis maintainer (PR #131580)
Aiden Grossman via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Matt Arsenault via llvm-commits
- [llvm] [SeparateConstOffsetFromGEP] Don't set unsound inbounds flag (PR #130616)
Fabian Ritter via llvm-commits
- [llvm] [SeparateConstOffsetFromGEP] Don't set unsound inbounds flag (PR #130616)
Fabian Ritter via llvm-commits
- [llvm] [AMDGPU] Add identity_combines to RegBankCombiner (PR #131305)
Pierre van Houtryve via llvm-commits
- [llvm] a10e1e0 - [RISCV] Remove unused check prefixes from double maximum/minimum test. NFC
Jim Lin via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Matt Arsenault via llvm-commits
- [llvm] [Exegesis] CPU selection, when native arch and target mismatch (PR #131014)
Aiden Grossman via llvm-commits
- [llvm] [CodeGen] Add MachineRegisterClassInfo analysis pass (PR #120690)
Pengcheng Wang via llvm-commits
- [llvm] [MachineVerifier] Fix LiveInterval verification of unwinding instructions (PR #131565)
Heejin Ahn via llvm-commits
- [llvm] [AMDGPU] Add identity_combines to RegBankCombiner (PR #131305)
Pierre van Houtryve via llvm-commits
- [llvm] [CodeGen] Add MachineRegisterClassInfo analysis pass (PR #120690)
Pengcheng Wang via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Matt Arsenault via llvm-commits
- [llvm] [WebAssembly] Split separate component LiveIntervals for TEEs (PR #131561)
Heejin Ahn via llvm-commits
- [llvm] [AMDGPU] Add identity_combines to RegBankCombiner (PR #131305)
Pierre van Houtryve via llvm-commits
- [llvm] [LoongArch] Custom lower vector trunc to vector shuffle (PR #130938)
Lu Weining via llvm-commits
- [llvm] 8cc6c2e - AMDGPU: Migrate more tests away from undef (#131314)
via llvm-commits
- [llvm] AMDGPU: Migrate more tests away from undef (PR #131314)
Matt Arsenault via llvm-commits
- [llvm] AMDGPU: Switch test to generated checks (PR #131315)
Matt Arsenault via llvm-commits
- [llvm] AMDGPU: Switch test to generated checks (PR #131315)
Matt Arsenault via llvm-commits
- [llvm] [AMDGPU] Add identity_combines to RegBankCombiner (PR #131305)
Pierre van Houtryve via llvm-commits
- [llvm] [BOLT][AArch64] Do not crash on authenticated branch instructions (PR #129898)
Anatoly Trosinenko via llvm-commits
- [llvm] AMDGPU: Switch test to generated checks (PR #131315)
Matt Arsenault via llvm-commits
- [llvm] [mlir] [mlir][OpenMP] Add __atomic_store to AtomicInfo (PR #121055)
via llvm-commits
- [llvm] [AMDGPU] Add identity_combines to RegBankCombiner (PR #131305)
Pierre van Houtryve via llvm-commits
- [llvm] [SDAG] Handle extract_subvector in isKnownNeverNaN (PR #131581)
Jim Lin via llvm-commits
- [llvm] [llvm-exegesis] Add myself as an llvm-exegesis maintainer (PR #131580)
Guillaume Chatelet via llvm-commits
- [llvm] [SDAG] Handle extract_subvector in isKnownNeverNaN (PR #131581)
via llvm-commits
- [llvm] ee8a804 - AMDGPU: Switch test to generated checks (#131315)
via llvm-commits
- [llvm] AMDGPU: Switch test to generated checks (PR #131315)
Matt Arsenault via llvm-commits
- [llvm] AMDGPU: Switch scheduler-subrange-crash.ll to generated checks (PR #131316)
Matt Arsenault via llvm-commits
- [llvm] AMDGPU: Switch scheduler-subrange-crash.ll to generated checks (PR #131316)
Matt Arsenault via llvm-commits
- [llvm] [SDAG] Handle extract_subvector in isKnownNeverNaN (PR #131581)
Matt Arsenault via llvm-commits
- [llvm] [AMDGPU] Add identity_combines to RegBankCombiner (PR #131305)
Pierre van Houtryve via llvm-commits
- [llvm] [CrossDSO CFI] Make sure __cfi_check has BTI attribute. (PR #131224)
Daniel Kiss via llvm-commits
- [llvm] a6ae965 - AMDGPU: Switch scheduler-subrange-crash.ll to generated checks (#131316)
via llvm-commits
- [llvm] AMDGPU: Switch scheduler-subrange-crash.ll to generated checks (PR #131316)
Matt Arsenault via llvm-commits
- [llvm] AMDGPU: Switch simplifydemandedbits-recursion.ll to generated checks (PR #131317)
Matt Arsenault via llvm-commits
- [llvm] AMDGPU: Switch simplifydemandedbits-recursion.ll to generated checks (PR #131317)
Matt Arsenault via llvm-commits
- [llvm] [llvm-exegesis] Add myself as an llvm-exegesis maintainer (PR #131580)
via llvm-commits
- [llvm] [AMDGPU] Add identity_combines to RegBankCombiner (PR #131305)
Pierre van Houtryve via llvm-commits
- [llvm] [bindings] Add OCaml binding to `LLVMGlobalSetMetadata` (PR #131583)
Rynco Maekawa via llvm-commits
- [llvm] [bindings] Add OCaml binding to `LLVMGlobalSetMetadata` (PR #131583)
via llvm-commits
- [llvm] [Exegesis] CPU selection, when native arch and target mismatch (PR #131014)
via llvm-commits
- [llvm] 1f1f820 - AMDGPU: Switch simplifydemandedbits-recursion.ll to generated checks (#131317)
via llvm-commits
- [llvm] AMDGPU: Switch simplifydemandedbits-recursion.ll to generated checks (PR #131317)
Matt Arsenault via llvm-commits
- [llvm] [VPlan] Remove createReduction. NFCI (PR #131336)
David Sherwood via llvm-commits
- [llvm] 7dcea28 - [AMDGPU] Add identity_combines to RegBankCombiner (#131305)
via llvm-commits
- [llvm] [AMDGPU] Add identity_combines to RegBankCombiner (PR #131305)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU][RegBankInfo] Promote scalar i16 and/or/xor to i32 (PR #131306)
Pierre van Houtryve via llvm-commits
- [clang] [llvm] Define LLVM_ABI and CLANG_ABI for __EMSCRIPTEN__ builds (PR #131578)
Anutosh Bhat via llvm-commits
- [llvm] [AMDGPU][RegBankInfo] Promote scalar i16 and/or/xor to i32 (PR #131306)
Pierre van Houtryve via llvm-commits
- [llvm] [bindings] Add OCaml binding to `LLVMGlobalSetMetadata` (PR #131583)
Rynco Maekawa via llvm-commits
- [llvm] [llvm-exegesis] Add myself as an llvm-exegesis maintainer (PR #131580)
Clement Courbet via llvm-commits
- [llvm] [NFC][AArch64] test for sdiv with fixed-width vectors, pow2-divisor and SVE enabled (PR #130252)
Sushant Gokhale via llvm-commits
- [llvm] [AMDGPU][RegBankInfo] Promote scalar i16 and/or/xor to i32 (PR #131306)
Pierre van Houtryve via llvm-commits
- [llvm] [Exegesis] CPU selection, when native arch and target mismatch (PR #131014)
via llvm-commits
- [llvm] ab1dcac - [AMDGPU][RegBankInfo] Promote scalar i16 and/or/xor to i32 (#131306)
via llvm-commits
- [llvm] [AMDGPU][RegBankInfo] Promote scalar i16 and/or/xor to i32 (PR #131306)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU][RegBankCombiner] Add cast_of_cast and constant_fold_cast combines (PR #131307)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU][RegBankCombiner] Add cast_of_cast and constant_fold_cast combines (PR #131307)
Pierre van Houtryve via llvm-commits
- [llvm] [cmake] Move FindLibcCommonUtils to shared cmake, to fix standalone builds (PR #131586)
Michał Górny via llvm-commits
- [llvm] e456579 - [AMDGPU][RegBankCombiner] Add cast_of_cast and constant_fold_cast combines (#131307)
via llvm-commits
- [llvm] [AMDGPU][RegBankCombiner] Add cast_of_cast and constant_fold_cast combines (PR #131307)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU][Legalizer] Widen i16 G_SEXT_INREG (PR #131308)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU][Legalizer] Widen i16 G_SEXT_INREG (PR #131308)
Pierre van Houtryve via llvm-commits
- [llvm] [VPlan] Account for dead FOR splice simplification in cost model (PR #131486)
David Sherwood via llvm-commits
- [llvm] [LV][NFC] Pre-commit test for supporting strided accesses. (PR #130563)
Mel Chen via llvm-commits
- [llvm] [FileCheck] Avoid repeated hash lookups (NFC) (PR #131553)
Thomas Preud'homme via llvm-commits
- [llvm] 0878dd1 - [AArch64][GlobalISel] Add coverage for arm64-neon-2velem.ll. NFC
David Green via llvm-commits
- [llvm] [VPlan] Account for dead FOR splice simplification in cost model (PR #131486)
Mel Chen via llvm-commits
- [llvm] [VPlan] Account for dead FOR splice simplification in cost model (PR #131486)
Mel Chen via llvm-commits
- [llvm] [VPlan] Account for dead FOR splice simplification in cost model (PR #131486)
Mel Chen via llvm-commits
- [llvm] [SDAG] Handle extract_subvector in isKnownNeverNaN (PR #131581)
Pengcheng Wang via llvm-commits
- [llvm] [AMDGPU][CodeGen] Using MBB's liveIn check in tandem with MCRegAliasIterator in SILowerSGPRSpills (PR #129848)
Vikash Gupta via llvm-commits
- [llvm] [X86][NFC] Add missing immediate qualifier to VSM3RNDS2 instruction (PR #131576)
Simon Pilgrim via llvm-commits
- [llvm] [Aarch64] [ISel] Don't save vaargs registers if vaargs are unused (PR #126780)
Hans Wennborg via llvm-commits
- [llvm] [AMDGPU][CodeGen] Using MBB's liveIn check in tandem with MCRegAliasIterator in SILowerSGPRSpills (PR #129848)
Vikash Gupta via llvm-commits
- [llvm] Reapply "[Aarch64] [ISel] Don't save vaargs registers if vaargs are unused" (PR #131459)
Hans Wennborg via llvm-commits
- [llvm] AMDGPU: Move insertion into V2SCopies map (PR #130776)
Matt Arsenault via llvm-commits
- [llvm] 5c73c5c - [X86][NFC] Add missing immediate qualifier to VSM3RNDS2 instruction (#131576)
via llvm-commits
- [llvm] [X86][NFC] Add missing immediate qualifier to VSM3RNDS2 instruction (PR #131576)
Phoebe Wang via llvm-commits
- [llvm] [Transforms] Avoid repeated hash lookups (NFC) (PR #131554)
Nikita Popov via llvm-commits
- [llvm] [TargetParser] Avoid repeated hash lookups (NFC) (PR #131555)
Nikita Popov via llvm-commits
- [llvm] [Transforms] Avoid repeated hash lookups (NFC) (PR #131556)
Nikita Popov via llvm-commits
- [llvm] [CodeGen] Add MachineRegisterClassInfo analysis pass (PR #120690)
via llvm-commits
- [llvm] [CodeGen] Add MachineRegisterClassInfo analysis pass (PR #120690)
via llvm-commits
- [clang] [llvm] [BPF] Make -mcpu=v3 as the default (PR #107008)
Yuval Deutscher via llvm-commits
- [llvm] [SPIRV] Support for SPV_INTEL_cluster_attributes extension (PR #131593)
via llvm-commits
- [llvm] [SPIRV] Support for SPV_INTEL_cluster_attributes extension (PR #131593)
via llvm-commits
- [llvm] [SPIRV] Support for SPV_INTEL_cluster_attributes extension (PR #131593)
via llvm-commits
- [llvm] [LiveDebugValues][NFC] Remove TargetPassConfig from LDVImpl (PR #131562)
Jeremy Morse via llvm-commits
- [llvm] [AMDGPU] frame index elimination hit assertion for scavenged nonreg (PR #130287)
Pankaj Dwivedi via llvm-commits
- [llvm] [llvm][yaml2obj] Modify section header overriding timing (PR #130942)
Ruoyu Qiu via llvm-commits
- [llvm] [AArch64][SVE] Fold integer lane extract and store to FPR store (PR #129756)
Benjamin Maxwell via llvm-commits
- [llvm] [AArch64][SVE] Fold integer lane extract and store to FPR store (PR #129756)
Benjamin Maxwell via llvm-commits
- [llvm] [AArch64][SVE] Fold integer lane extract and store to FPR store (PR #129756)
Benjamin Maxwell via llvm-commits
- [llvm] [LLVM][PDB] Use IsUnsigned flag for APInt correctly (PR #131598)
Aleksandr Korepanov via llvm-commits
- [llvm] [LLVM][PDB] Use IsUnsigned flag for APInt correctly (PR #131598)
via llvm-commits
- [llvm] [LLVM][PDB] Use IsUnsigned flag for APInt correctly (PR #131598)
Aleksandr Korepanov via llvm-commits
- [llvm] [VPlan] Change parent of VPReductionRecipe to VPRecipeWithIRFlags. NFC (PR #130881)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Change parent of VPReductionRecipe to VPRecipeWithIRFlags. NFC (PR #130881)
Florian Hahn via llvm-commits
- [llvm] [AMDGPU][MC] Support UC_VERSION_* constants. (PR #95618)
Ivan Kosarev via llvm-commits
- [clang] [llvm] [BPF] Make -mcpu=v3 as the default (PR #107008)
Yuval Deutscher via llvm-commits
- [llvm] [LiveDebugValues][NFC] Remove TargetPassConfig from LDVImpl (PR #131562)
Akshat Oke via llvm-commits
- [llvm] [BOLT] Enable hugify for AArch64 (PR #117158)
via llvm-commits
- [llvm] [LiveDebugValues][NFC] Remove TargetPassConfig from LDVImpl (PR #131562)
Akshat Oke via llvm-commits
- [llvm] [llvm][yaml2obj] Modify section header overriding timing (PR #130942)
Ruoyu Qiu via llvm-commits
- [llvm] [AMDGPU] Support block load/store for CSR (PR #130013)
Diana Picus via llvm-commits
- [llvm] [AMDGPU] Add SubtargetFeature for dynamic VGPR mode (PR #130030)
Diana Picus via llvm-commits
- [llvm] 8c939f5 - [WebAssembly] Change placeholder from `undef` to `poison` (#131536)
via llvm-commits
- [llvm] [WebAssembly] Change placeholder from `undef` to `poison` (PR #131536)
Pedro Lobo via llvm-commits
- [llvm] [VPlan] Remove createReduction. NFCI (PR #131336)
Luke Lau via llvm-commits
- [llvm] [VPlan] Remove createReduction. NFCI (PR #131336)
Luke Lau via llvm-commits
- [llvm] [AArch64][SVE] Fold integer lane extract and store to FPR store (PR #129756)
Sander de Smalen via llvm-commits
- [llvm] [LiveDebugValues][NFC] Remove TargetPassConfig from LDVImpl (PR #131562)
Matt Arsenault via llvm-commits
- [llvm] [BOLT] Enable hugify for AArch64 (PR #117158)
Paschalis Mpeis via llvm-commits
- [llvm] [VPlan] Change parent of VPReductionRecipe to VPRecipeWithIRFlags. NFC (PR #130881)
Luke Lau via llvm-commits
- [llvm] Update the base and index value for masked gather (PR #130920)
Rohit Aggarwal via llvm-commits
- [llvm] [VPlan] Account for dead FOR splice simplification in cost model (PR #131486)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Account for dead FOR splice simplification in cost model (PR #131486)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Account for dead FOR splice simplification in cost model (PR #131486)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Account for dead FOR splice simplification in cost model (PR #131486)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Account for dead FOR splice simplification in cost model (PR #131486)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Account for dead FOR splice simplification in cost model (PR #131486)
Luke Lau via llvm-commits
- [llvm] [AMDGPU] Implement IR expansion for frem instruction (PR #130988)
Frederik Harwath via llvm-commits
- [llvm] [VPlan] Change parent of VPReductionRecipe to VPRecipeWithIRFlags. NFC (PR #130881)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Account for dead FOR splice simplification in cost model (PR #131486)
Luke Lau via llvm-commits
- [llvm] [docs] Mention --discard-locals/--discard-all change for llvm-strip (PR #131491)
Andrew Ng via llvm-commits
- [llvm] [docs] Mention --discard-locals/--discard-all change for llvm-strip (PR #131491)
Andrew Ng via llvm-commits
- [llvm] [docs] Mention --discard-locals/--discard-all change for llvm-strip (PR #131491)
Andrew Ng via llvm-commits
- [llvm] [LV] Optimize VPWidenIntOrFpInductionRecipe for known TC (PR #118828)
Florian Hahn via llvm-commits
- [llvm] [LV] Optimize VPWidenIntOrFpInductionRecipe for known TC (PR #118828)
Florian Hahn via llvm-commits
- [llvm] [LV] Optimize VPWidenIntOrFpInductionRecipe for known TC (PR #118828)
Florian Hahn via llvm-commits
- [llvm] [LV] Optimize VPWidenIntOrFpInductionRecipe for known TC (PR #118828)
Florian Hahn via llvm-commits
- [llvm] [LV] Optimize VPWidenIntOrFpInductionRecipe for known TC (PR #118828)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Account for dead FOR splice simplification in cost model (PR #131486)
Luke Lau via llvm-commits
- [llvm] [VPlan] Change parent of VPReductionRecipe to VPRecipeWithIRFlags. NFC (PR #130881)
Luke Lau via llvm-commits
- [llvm] [AMDGPU] Implement IR expansion for frem instruction (PR #130988)
Frederik Harwath via llvm-commits
- [llvm] e57cd10 - Define LLVM_ABI and CLANG_ABI for __EMSCRIPTEN__ builds (#131578)
via llvm-commits
- [clang] [llvm] Define LLVM_ABI and CLANG_ABI for __EMSCRIPTEN__ builds (PR #131578)
via llvm-commits
- [llvm] Update the base and index value for masked gather (PR #130920)
Rohit Aggarwal via llvm-commits
- [llvm] [AMDGPU] Improve StructurizeCFG pass performance by using SSAUpdaterBulk. (PR #130611)
Matt Arsenault via llvm-commits
- [llvm] Update the base and index value for masked gather (PR #130920)
Rohit Aggarwal via llvm-commits
- [llvm] [mlir] [MLIR][OpenMP] Lowering nontemporal clause to LLVM IR for SIMD directive (PR #118751)
Tom Eccles via llvm-commits
- [llvm] [VPlan] Change parent of VPReductionRecipe to VPRecipeWithIRFlags. NFC (PR #130881)
Florian Hahn via llvm-commits
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Luke Lau via llvm-commits
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Archived on: Sun Mar 23 23:58:48 PDT 2025
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