[clang] [llvm] [X86][AVX10.2] Remove YMM rounding from VCVTTP.*QS (PR #132414)
Phoebe Wang via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 21 09:58:40 PDT 2025
https://github.com/phoebewang updated https://github.com/llvm/llvm-project/pull/132414
>From 096e0b112724176f3d4893657580588a021d2224 Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe" <phoebe.wang at intel.com>
Date: Fri, 21 Mar 2025 23:53:15 +0800
Subject: [PATCH 1/2] [X86][AVX10.2] Remove YMM rounding from VCVTTP.*QS
Ref: https://cdrdv2.intel.com/v1/dl/getContent/784343
---
clang/include/clang/Basic/BuiltinsX86.td | 16 +-
clang/lib/Headers/avx10_2satcvtdsintrin.h | 220 ++++--------------
clang/lib/Sema/SemaX86.cpp | 8 -
.../X86/avx10_2satcvtds-builtins-errors.c | 57 -----
.../X86/avx10_2satcvtds-builtins-x64.c | 96 +-------
.../CodeGen/X86/avx10_2satcvtds-builtins.c | 103 ++------
llvm/include/llvm/IR/IntrinsicsX86.td | 48 ++--
llvm/lib/Target/X86/X86InstrAVX10.td | 5 -
llvm/lib/Target/X86/X86IntrinsicsInfo.h | 32 +--
.../CodeGen/X86/avx10_2satcvtds-intrinsics.ll | 76 +++---
.../Disassembler/X86/avx10.2-satcvtds-32.txt | 48 ----
.../Disassembler/X86/avx10.2-satcvtds-64.txt | 48 ----
llvm/test/MC/X86/avx10_2satcvtds-32-att.s | 48 ----
llvm/test/MC/X86/avx10_2satcvtds-32-intel.s | 64 -----
llvm/test/MC/X86/avx10_2satcvtds-64-att.s | 48 ----
llvm/test/MC/X86/avx10_2satcvtds-64-intel.s | 64 -----
16 files changed, 160 insertions(+), 821 deletions(-)
delete mode 100644 clang/test/CodeGen/X86/avx10_2satcvtds-builtins-errors.c
diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td
index ea0d6df4a33c2..583f4534dfab2 100644
--- a/clang/include/clang/Basic/BuiltinsX86.td
+++ b/clang/include/clang/Basic/BuiltinsX86.td
@@ -4615,7 +4615,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvttpd2dqs256_round_mask : X86Builtin<"_Vector<4, int>(_Vector<4, double>, _Vector<4, int>, unsigned char, _Constant int)">;
+ def vcvttpd2dqs256_mask : X86Builtin<"_Vector<4, int>(_Vector<4, double>, _Vector<4, int>, unsigned char)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
@@ -4627,7 +4627,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvttpd2udqs256_round_mask : X86Builtin<"_Vector<4, int>(_Vector<4, double>, _Vector<4, int>, unsigned char, _Constant int)">;
+ def vcvttpd2udqs256_mask : X86Builtin<"_Vector<4, int>(_Vector<4, double>, _Vector<4, int>, unsigned char)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
@@ -4639,7 +4639,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvttpd2qqs256_round_mask : X86Builtin<"_Vector<4, long long int>(_Vector<4, double>, _Vector<4, long long int>, unsigned char, _Constant int)">;
+ def vcvttpd2qqs256_mask : X86Builtin<"_Vector<4, long long int>(_Vector<4, double>, _Vector<4, long long int>, unsigned char)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
@@ -4651,7 +4651,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvttpd2uqqs256_round_mask : X86Builtin<"_Vector<4, long long int>(_Vector<4, double>, _Vector<4, long long int>, unsigned char, _Constant int)">;
+ def vcvttpd2uqqs256_mask : X86Builtin<"_Vector<4, long long int>(_Vector<4, double>, _Vector<4, long long int>, unsigned char)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
@@ -4663,7 +4663,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvttps2dqs256_round_mask : X86Builtin<"_Vector<8, int>(_Vector<8, float>, _Vector<8, int>, unsigned char, _Constant int)">;
+ def vcvttps2dqs256_mask : X86Builtin<"_Vector<8, int>(_Vector<8, float>, _Vector<8, int>, unsigned char)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
@@ -4675,7 +4675,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvttps2udqs256_round_mask : X86Builtin<"_Vector<8, int>(_Vector<8, float>, _Vector<8, int>, unsigned char, _Constant int)">;
+ def vcvttps2udqs256_mask : X86Builtin<"_Vector<8, int>(_Vector<8, float>, _Vector<8, int>, unsigned char)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
@@ -4687,7 +4687,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvttps2qqs256_round_mask : X86Builtin<"_Vector<4, long long int>(_Vector<4, float>, _Vector<4, long long int>, unsigned char, _Constant int)">;
+ def vcvttps2qqs256_mask : X86Builtin<"_Vector<4, long long int>(_Vector<4, float>, _Vector<4, long long int>, unsigned char)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
@@ -4699,7 +4699,7 @@ let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] i
}
let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in {
- def vcvttps2uqqs256_round_mask : X86Builtin<"_Vector<4, long long int>(_Vector<4, float>, _Vector<4, long long int>, unsigned char, _Constant int)">;
+ def vcvttps2uqqs256_mask : X86Builtin<"_Vector<4, long long int>(_Vector<4, float>, _Vector<4, long long int>, unsigned char)">;
}
let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in {
diff --git a/clang/lib/Headers/avx10_2satcvtdsintrin.h b/clang/lib/Headers/avx10_2satcvtdsintrin.h
index 9dbfed42667ef..6509a4ebf9c77 100644
--- a/clang/lib/Headers/avx10_2satcvtdsintrin.h
+++ b/clang/lib/Headers/avx10_2satcvtdsintrin.h
@@ -92,37 +92,22 @@ _mm_maskz_cvtts_pd_epi32(__mmask16 __U, __m128d __A) {
// 256 Bit : Double -> int
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtts_pd_epi32(__m256d __A) {
- return ((__m128i)__builtin_ia32_vcvttpd2dqs256_round_mask(
- (__v4df)__A, (__v4si)_mm_undefined_si128(), (__mmask8)-1,
- _MM_FROUND_CUR_DIRECTION));
+ return ((__m128i)__builtin_ia32_vcvttpd2dqs256_mask(
+ (__v4df)__A, (__v4si)_mm_undefined_si128(), (__mmask8)-1));
}
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_pd_epi32(__m128i __W, __mmask8 __U, __m256d __A) {
- return ((__m128i)__builtin_ia32_vcvttpd2dqs256_round_mask(
- (__v4df)__A, (__v4si)__W, __U, _MM_FROUND_CUR_DIRECTION));
+ return ((__m128i)__builtin_ia32_vcvttpd2dqs256_mask(
+ (__v4df)__A, (__v4si)__W, __U));
}
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtts_pd_epi32(__mmask8 __U, __m256d __A) {
- return ((__m128i)__builtin_ia32_vcvttpd2dqs256_round_mask(
- (__v4df)__A, (__v4si)_mm_setzero_si128(), __U, _MM_FROUND_CUR_DIRECTION));
+ return ((__m128i)__builtin_ia32_vcvttpd2dqs256_mask(
+ (__v4df)__A, (__v4si)_mm_setzero_si128(), __U));
}
-#define _mm256_cvtts_roundpd_epi32(__A, __R) \
- ((__m128i)__builtin_ia32_vcvttpd2dqs256_round_mask( \
- (__v4df)(__m256d)__A, (__v4si)(__m128i)_mm_undefined_si128(), \
- (__mmask8) - 1, (int)(__R)))
-
-#define _mm256_mask_cvtts_roundpd_epi32(__W, __U, __A, __R) \
- ((__m128i)__builtin_ia32_vcvttpd2dqs256_round_mask( \
- (__v4df)(__m256d)__A, (__v4si)(__m128i)__W, (__mmask8)__U, (int)(__R)))
-
-#define _mm256_maskz_cvtts_roundpd_epi32(__U, __A, __R) \
- ((__m128i)__builtin_ia32_vcvttpd2dqs256_round_mask( \
- (__v4df)(__m256d)__A, (__v4si)(__m128i)_mm_setzero_si128(), \
- (__mmask8)__U, (int)(__R)))
-
// 128 Bit : Double -> uint
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtts_pd_epu32(__m128d __A) {
@@ -145,37 +130,22 @@ _mm_maskz_cvtts_pd_epu32(__mmask8 __U, __m128d __A) {
// 256 Bit : Double -> uint
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtts_pd_epu32(__m256d __A) {
- return ((__m128i)__builtin_ia32_vcvttpd2udqs256_round_mask(
- (__v4df)__A, (__v4si)_mm_undefined_si128(), (__mmask8)-1,
- _MM_FROUND_CUR_DIRECTION));
+ return ((__m128i)__builtin_ia32_vcvttpd2udqs256_mask(
+ (__v4df)__A, (__v4si)_mm_undefined_si128(), (__mmask8)-1));
}
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_pd_epu32(__m128i __W, __mmask8 __U, __m256d __A) {
- return ((__m128i)__builtin_ia32_vcvttpd2udqs256_round_mask(
- (__v4df)__A, (__v4si)__W, __U, _MM_FROUND_CUR_DIRECTION));
+ return ((__m128i)__builtin_ia32_vcvttpd2udqs256_mask(
+ (__v4df)__A, (__v4si)__W, __U));
}
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtts_pd_epu32(__mmask8 __U, __m256d __A) {
- return ((__m128i)__builtin_ia32_vcvttpd2udqs256_round_mask(
- (__v4df)__A, (__v4si)_mm_setzero_si128(), __U, _MM_FROUND_CUR_DIRECTION));
+ return ((__m128i)__builtin_ia32_vcvttpd2udqs256_mask(
+ (__v4df)__A, (__v4si)_mm_setzero_si128(), __U));
}
-#define _mm256_cvtts_roundpd_epu32(__A, __R) \
- ((__m128i)__builtin_ia32_vcvttpd2udqs256_round_mask( \
- (__v4df)(__m256d)__A, (__v4si)(__m128i)_mm_undefined_si128(), \
- (__mmask8) - 1, (int)(__R)))
-
-#define _mm256_mask_cvtts_roundpd_epu32(__W, __U, __A, __R) \
- ((__m128i)__builtin_ia32_vcvttpd2udqs256_round_mask( \
- (__v4df)(__m256d)__A, (__v4si)(__m128i)__W, (__mmask8)__U, (int)(__R)))
-
-#define _mm256_maskz_cvtts_roundpd_epu32(__U, __A, __R) \
- ((__m128i)__builtin_ia32_vcvttpd2udqs256_round_mask( \
- (__v4df)(__m256d)__A, (__v4si)(__m128i)_mm_setzero_si128(), \
- (__mmask8)__U, (int)(__R)))
-
// 128 Bit : Double -> long
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtts_pd_epi64(__m128d __A) {
@@ -198,37 +168,22 @@ _mm_maskz_cvtts_pd_epi64(__mmask8 __U, __m128d __A) {
// 256 Bit : Double -> long
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_cvtts_pd_epi64(__m256d __A) {
- return ((__m256i)__builtin_ia32_vcvttpd2qqs256_round_mask(
- (__v4df)__A, (__v4di)_mm256_undefined_si256(), (__mmask8)-1,
- _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttpd2qqs256_mask(
+ (__v4df)__A, (__v4di)_mm256_undefined_si256(), (__mmask8)-1));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_pd_epi64(__m256i __W, __mmask8 __U, __m256d __A) {
- return ((__m256i)__builtin_ia32_vcvttpd2qqs256_round_mask(
- (__v4df)__A, (__v4di)__W, __U, _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttpd2qqs256_mask(
+ (__v4df)__A, (__v4di)__W, __U));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtts_pd_epi64(__mmask8 __U, __m256d __A) {
- return ((__m256i)__builtin_ia32_vcvttpd2qqs256_round_mask(
- (__v4df)__A, (__v4di)_mm256_setzero_si256(), __U,
- _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttpd2qqs256_mask(
+ (__v4df)__A, (__v4di)_mm256_setzero_si256(), __U));
}
-#define _mm256_cvtts_roundpd_epi64(__A, __R) \
- ((__m256i)__builtin_ia32_vcvttpd2qqs256_round_mask( \
- (__v4df)__A, (__v4di)_mm256_undefined_si256(), (__mmask8) - 1, \
- (int)__R))
-
-#define _mm256_mask_cvtts_roundpd_epi64(__W, __U, __A, __R) \
- ((__m256i)__builtin_ia32_vcvttpd2qqs256_round_mask((__v4df)__A, (__v4di)__W, \
- (__mmask8)__U, (int)__R))
-
-#define _mm256_maskz_cvtts_roundpd_epi64(__U, __A, __R) \
- ((__m256i)__builtin_ia32_vcvttpd2qqs256_round_mask( \
- (__v4df)__A, (__v4di)_mm256_setzero_si256(), (__mmask8)__U, (int)__R))
-
// 128 Bit : Double -> ulong
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtts_pd_epu64(__m128d __A) {
@@ -252,37 +207,22 @@ _mm_maskz_cvtts_pd_epu64(__mmask8 __U, __m128d __A) {
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_cvtts_pd_epu64(__m256d __A) {
- return ((__m256i)__builtin_ia32_vcvttpd2uqqs256_round_mask(
- (__v4df)__A, (__v4di)_mm256_undefined_si256(), (__mmask8)-1,
- _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttpd2uqqs256_mask(
+ (__v4df)__A, (__v4di)_mm256_undefined_si256(), (__mmask8)-1));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_pd_epu64(__m256i __W, __mmask8 __U, __m256d __A) {
- return ((__m256i)__builtin_ia32_vcvttpd2uqqs256_round_mask(
- (__v4df)__A, (__v4di)__W, __U, _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttpd2uqqs256_mask(
+ (__v4df)__A, (__v4di)__W, __U));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtts_pd_epu64(__mmask8 __U, __m256d __A) {
- return ((__m256i)__builtin_ia32_vcvttpd2uqqs256_round_mask(
- (__v4df)__A, (__v4di)_mm256_setzero_si256(), __U,
- _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttpd2uqqs256_mask(
+ (__v4df)__A, (__v4di)_mm256_setzero_si256(), __U));
}
-#define _mm256_cvtts_roundpd_epu64(__A, __R) \
- ((__m256i)__builtin_ia32_vcvttpd2uqqs256_round_mask( \
- (__v4df)__A, (__v4di)_mm256_undefined_si256(), (__mmask8) - 1, \
- (int)__R))
-
-#define _mm256_mask_cvtts_roundpd_epu64(__W, __U, __A, __R) \
- ((__m256i)__builtin_ia32_vcvttpd2uqqs256_round_mask( \
- (__v4df)__A, (__v4di)__W, (__mmask8)__U, (int)__R))
-
-#define _mm256_maskz_cvtts_roundpd_epu64(__U, __A, __R) \
- ((__m256i)__builtin_ia32_vcvttpd2uqqs256_round_mask( \
- (__v4df)__A, (__v4di)_mm256_setzero_si256(), (__mmask8)__U, (int)__R))
-
// 128 Bit : float -> int
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtts_ps_epi32(__m128 __A) {
return ((__m128i)__builtin_ia32_vcvttps2dqs128_mask(
@@ -304,38 +244,22 @@ _mm_maskz_cvtts_ps_epi32(__mmask8 __U, __m128 __A) {
// 256 Bit : float -> int
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_cvtts_ps_epi32(__m256 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2dqs256_round_mask(
- (__v8sf)__A, (__v8si)_mm256_undefined_si256(), (__mmask8)-1,
- _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttps2dqs256_mask(
+ (__v8sf)__A, (__v8si)_mm256_undefined_si256(), (__mmask8)-1));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_ps_epi32(__m256i __W, __mmask8 __U, __m256 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2dqs256_round_mask(
- (__v8sf)__A, (__v8si)__W, __U, _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttps2dqs256_mask(
+ (__v8sf)__A, (__v8si)__W, __U));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtts_ps_epi32(__mmask8 __U, __m256 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2dqs256_round_mask(
- (__v8sf)__A, (__v8si)_mm256_setzero_si256(), __U,
- _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttps2dqs256_mask(
+ (__v8sf)__A, (__v8si)_mm256_setzero_si256(), __U));
}
-#define _mm256_cvtts_roundps_epi32(__A, __R) \
- ((__m256i)__builtin_ia32_vcvttps2dqs256_round_mask( \
- (__v8sf)(__m256)__A, (__v8si)(__m256i)_mm256_undefined_si256(), \
- (__mmask8) - 1, (int)(__R)))
-
-#define _mm256_mask_cvtts_roundps_epi32(__W, __U, __A, __R) \
- ((__m256i)__builtin_ia32_vcvttps2dqs256_round_mask( \
- (__v8sf)(__m256)__A, (__v8si)(__m256i)__W, (__mmask8)__U, (int)(__R)))
-
-#define _mm256_maskz_cvtts_roundps_epi32(__U, __A, __R) \
- ((__m256i)__builtin_ia32_vcvttps2dqs256_round_mask( \
- (__v8sf)(__m256)__A, (__v8si)(__m256i)_mm256_setzero_si256(), \
- (__mmask8)__U, (int)(__R)))
-
// 128 Bit : float -> uint
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtts_ps_epu32(__m128 __A) {
return ((__m128i)__builtin_ia32_vcvttps2udqs128_mask(
@@ -358,38 +282,22 @@ _mm_maskz_cvtts_ps_epu32(__mmask8 __U, __m128 __A) {
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_cvtts_ps_epu32(__m256 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2udqs256_round_mask(
- (__v8sf)__A, (__v8si)_mm256_undefined_si256(), (__mmask8)-1,
- _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttps2udqs256_mask(
+ (__v8sf)__A, (__v8si)_mm256_undefined_si256(), (__mmask8)-1));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_ps_epu32(__m256i __W, __mmask8 __U, __m256 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2udqs256_round_mask(
- (__v8sf)__A, (__v8si)__W, __U, _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttps2udqs256_mask(
+ (__v8sf)__A, (__v8si)__W, __U));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtts_ps_epu32(__mmask8 __U, __m256 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2udqs256_round_mask(
- (__v8sf)__A, (__v8si)_mm256_setzero_si256(), __U,
- _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttps2udqs256_mask(
+ (__v8sf)__A, (__v8si)_mm256_setzero_si256(), __U));
}
-#define _mm256_cvtts_roundps_epu32(__A, __R) \
- ((__m256i)__builtin_ia32_vcvttps2udqs256_round_mask( \
- (__v8sf)(__m256)__A, (__v8si)(__m256i)_mm256_undefined_si256(), \
- (__mmask8) - 1, (int)(__R)))
-
-#define _mm256_mask_cvtts_roundps_epu32(__W, __U, __A, __R) \
- ((__m256i)__builtin_ia32_vcvttps2udqs256_round_mask( \
- (__v8sf)(__m256)__A, (__v8si)(__m256i)__W, (__mmask8)__U, (int)(__R)))
-
-#define _mm256_maskz_cvtts_roundps_epu32(__U, __A, __R) \
- ((__m256i)__builtin_ia32_vcvttps2udqs256_round_mask( \
- (__v8sf)(__m256)__A, (__v8si)(__m256i)_mm256_setzero_si256(), \
- (__mmask8)__U, (int)(__R)))
-
// 128 bit : float -> long
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtts_ps_epi64(__m128 __A) {
return ((__m128i)__builtin_ia32_vcvttps2qqs128_mask(
@@ -411,37 +319,21 @@ _mm_maskz_cvtts_ps_epi64(__mmask8 __U, __m128 __A) {
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_cvtts_ps_epi64(__m128 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2qqs256_round_mask(
- (__v4sf)__A, (__v4di)_mm256_undefined_si256(), (__mmask8)-1,
- _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttps2qqs256_mask(
+ (__v4sf)__A, (__v4di)_mm256_undefined_si256(), (__mmask8)-1));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_ps_epi64(__m256i __W, __mmask8 __U, __m128 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2qqs256_round_mask(
- (__v4sf)__A, (__v4di)__W, __U, _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttps2qqs256_mask(
+ (__v4sf)__A, (__v4di)__W, __U));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtts_ps_epi64(__mmask8 __U, __m128 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2qqs256_round_mask(
- (__v4sf)__A, (__v4di)_mm256_setzero_si256(), __U,
- _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttps2qqs256_mask(
+ (__v4sf)__A, (__v4di)_mm256_setzero_si256(), __U));
}
-#define _mm256_cvtts_roundps_epi64(__A, __R) \
- ((__m256i)__builtin_ia32_vcvttps2qqs256_round_mask( \
- (__v4sf)(__m128)__A, (__v4di)_mm256_undefined_si256(), (__mmask8) - 1, \
- (int)__R))
-
-#define _mm256_mask_cvtts_roundps_epi64(__W, __U, __A, __R) \
- ((__m256i)__builtin_ia32_vcvttps2qqs256_round_mask( \
- (__v4sf)(__m128)__A, (__v4di)__W, (__mmask8)__U, (int)__R))
-
-#define _mm256_maskz_cvtts_roundps_epi64(__U, __A, __R) \
- ((__m256i)__builtin_ia32_vcvttps2qqs256_round_mask( \
- (__v4sf)(__m128)__A, (__v4di)_mm256_setzero_si256(), (__mmask8)__U, \
- (int)__R))
-
// 128 bit : float -> ulong
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtts_ps_epu64(__m128 __A) {
return ((__m128i)__builtin_ia32_vcvttps2uqqs128_mask(
@@ -463,38 +355,22 @@ _mm_maskz_cvtts_ps_epu64(__mmask8 __U, __m128 __A) {
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_cvtts_ps_epu64(__m128 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2uqqs256_round_mask(
- (__v4sf)__A, (__v4di)_mm256_undefined_si256(), (__mmask8)-1,
- _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttps2uqqs256_mask(
+ (__v4sf)__A, (__v4di)_mm256_undefined_si256(), (__mmask8)-1));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_ps_epu64(__m256i __W, __mmask8 __U, __m128 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2uqqs256_round_mask(
- (__v4sf)__A, (__v4di)__W, __U, _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttps2uqqs256_mask(
+ (__v4sf)__A, (__v4di)__W, __U));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtts_ps_epu64(__mmask8 __U, __m128 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2uqqs256_round_mask(
- (__v4sf)__A, (__v4di)_mm256_setzero_si256(), __U,
- _MM_FROUND_CUR_DIRECTION));
+ return ((__m256i)__builtin_ia32_vcvttps2uqqs256_mask(
+ (__v4sf)__A, (__v4di)_mm256_setzero_si256(), __U));
}
-#define _mm256_cvtts_roundps_epu64(__A, __R) \
- ((__m256i)__builtin_ia32_vcvttps2uqqs256_round_mask( \
- (__v4sf)(__m128)__A, (__v4di)_mm256_undefined_si256(), (__mmask8) - 1, \
- (int)__R))
-
-#define _mm256_mask_cvtts_roundps_epu64(__W, __U, __A, __R) \
- ((__m256i)__builtin_ia32_vcvttps2uqqs256_round_mask( \
- (__v4sf)(__m128)__A, (__v4di)__W, (__mmask8)__U, (int)__R))
-
-#define _mm256_maskz_cvtts_roundps_epu64(__U, __A, __R) \
- ((__m256i)__builtin_ia32_vcvttps2uqqs256_round_mask( \
- (__v4sf)(__m128)__A, (__v4di)_mm256_setzero_si256(), (__mmask8)__U, \
- (int)__R))
-
#undef __DEFAULT_FN_ATTRS128
#undef __DEFAULT_FN_ATTRS256
#endif // __AVX10_2SATCVTDSINTRIN_H
diff --git a/clang/lib/Sema/SemaX86.cpp b/clang/lib/Sema/SemaX86.cpp
index e54a278225f1c..32ab8357fd8e7 100644
--- a/clang/lib/Sema/SemaX86.cpp
+++ b/clang/lib/Sema/SemaX86.cpp
@@ -319,21 +319,13 @@ bool SemaX86::CheckBuiltinRoundingOrSAE(unsigned BuiltinID, CallExpr *TheCall) {
ArgNum = 4;
HasRC = true;
break;
- case X86::BI__builtin_ia32_vcvttpd2dqs256_round_mask:
case X86::BI__builtin_ia32_vcvttpd2dqs512_round_mask:
- case X86::BI__builtin_ia32_vcvttpd2udqs256_round_mask:
case X86::BI__builtin_ia32_vcvttpd2udqs512_round_mask:
- case X86::BI__builtin_ia32_vcvttpd2qqs256_round_mask:
case X86::BI__builtin_ia32_vcvttpd2qqs512_round_mask:
- case X86::BI__builtin_ia32_vcvttpd2uqqs256_round_mask:
case X86::BI__builtin_ia32_vcvttpd2uqqs512_round_mask:
- case X86::BI__builtin_ia32_vcvttps2dqs256_round_mask:
case X86::BI__builtin_ia32_vcvttps2dqs512_round_mask:
- case X86::BI__builtin_ia32_vcvttps2udqs256_round_mask:
case X86::BI__builtin_ia32_vcvttps2udqs512_round_mask:
- case X86::BI__builtin_ia32_vcvttps2qqs256_round_mask:
case X86::BI__builtin_ia32_vcvttps2qqs512_round_mask:
- case X86::BI__builtin_ia32_vcvttps2uqqs256_round_mask:
case X86::BI__builtin_ia32_vcvttps2uqqs512_round_mask:
ArgNum = 3;
break;
diff --git a/clang/test/CodeGen/X86/avx10_2satcvtds-builtins-errors.c b/clang/test/CodeGen/X86/avx10_2satcvtds-builtins-errors.c
deleted file mode 100644
index f32dfba60132d..0000000000000
--- a/clang/test/CodeGen/X86/avx10_2satcvtds-builtins-errors.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i386-unknown-unknown -target-feature +avx10.2-256 -Wall -Werror -verify
-
-unsigned long long test_mm_cvttssd(unsigned long long __A) {
- return _mm_cvttssd(__A); // expected-error {{call to undeclared function '_mm_cvttssd'}}
-}
-
-unsigned long long test_mm_cvttsss(unsigned long long __A) {
- return _mm_cvttsss(__A); // expected-error {{call to undeclared function '_mm_cvttsss'}}
-}
-
-#include <immintrin.h>
-#include <stddef.h>
-
-__m128i test_mm256_cvtts_roundpd_epi32(__m256d A) {
- return _mm256_cvtts_roundpd_epi32(A, 22); // expected-error {{invalid rounding argument}}
-}
-__m128i test_mm256_mask_cvtts_roundpd_epi32(__m128i W, __mmask8 U, __m256d A) {
- return _mm256_mask_cvtts_roundpd_epi32(W, U, A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m128i test_mm256_maskz_cvtts_roundpd_epi32(__mmask8 U, __m256d A) {
- return _mm256_maskz_cvtts_roundpd_epi32(U, A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m128i test_mm256_cvtts_roundpd_epu32(__m256d A) {
- return _mm256_cvtts_roundpd_epu32(A, 22); // expected-error {{invalid rounding argument}}
-}
-__m128i test_mm256_mask_cvtts_roundpd_epu32(__m128i W, __mmask8 U, __m256d A) {
- return _mm256_mask_cvtts_roundpd_epu32(W, U, A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m128i test_mm256_maskz_cvtts_roundpd_epu32(__mmask8 U, __m256d A) {
- return _mm256_maskz_cvtts_roundpd_epu32(U, A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_cvtts_roundps_epi32(__m256 A) {
- return _mm256_cvtts_roundps_epi32(A, 22); // expected-error {{invalid rounding argument}}
-}
-__m256i test_mm256_mask_cvtts_roundps_epi32(__m256i W, __mmask8 U, __m256 A) {
- return _mm256_mask_cvtts_roundps_epi32(W, U, A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_maskz_cvtts_roundps_epi32(__mmask8 U, __m256 A) {
- return _mm256_maskz_cvtts_roundps_epi32(U, A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_cvtts_roundps_epu32(__m256 A) {
- return _mm256_cvtts_roundps_epu32(A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_mask_cvtts_roundps_epu32(__m256i W, __mmask8 U, __m256 A) {
- return _mm256_mask_cvtts_roundps_epu32(W, U, A, 22); // expected-error {{invalid rounding argument}}
-}
-
-__m256i test_mm256_maskz_cvtts_roundps_epu32(__mmask8 U, __m256 A) {
- return _mm256_maskz_cvtts_roundps_epu32(U, A, 22); // expected-error {{invalid rounding argument}}
-}
diff --git a/clang/test/CodeGen/X86/avx10_2satcvtds-builtins-x64.c b/clang/test/CodeGen/X86/avx10_2satcvtds-builtins-x64.c
index 73eeb8484efb8..070065228e5a5 100644
--- a/clang/test/CodeGen/X86/avx10_2satcvtds-builtins-x64.c
+++ b/clang/test/CodeGen/X86/avx10_2satcvtds-builtins-x64.c
@@ -82,76 +82,40 @@ __m128i test_mm_maskz_cvtts_pd_epu64(__mmask8 U,__m128d A){
// 256 bit
__m256i test_mm256_cvtts_pd_epi64(__m256d A){
// CHECK-LABEL: @test_mm256_cvtts_pd_epi64
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2qqs.round.256(<4 x double>
+// CHECK: @llvm.x86.avx10.mask.vcvttpd2qqs.256(<4 x double>
return _mm256_cvtts_pd_epi64(A);
}
__m256i test_mm256_mask_cvtts_pd_epi64(__m256i W,__mmask8 U, __m256d A){
// CHECK-LABEL: @test_mm256_mask_cvtts_pd_epi64
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2qqs.round.256(<4 x double>
+// CHECK: @llvm.x86.avx10.mask.vcvttpd2qqs.256(<4 x double>
return _mm256_mask_cvtts_pd_epi64(W,U, A);
}
__m256i test_mm256_maskz_cvtts_pd_epi64(__mmask8 U, __m256d A){
// CHECK-LABEL: @test_mm256_maskz_cvtts_pd_epi64
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2qqs.round.256(<4 x double>
+// CHECK: @llvm.x86.avx10.mask.vcvttpd2qqs.256(<4 x double>
return _mm256_maskz_cvtts_pd_epi64(U, A);
}
-__m256i test_mm256_cvtts_roundpd_epi64(__m256d A){
-// CHECK-LABEL: @test_mm256_cvtts_roundpd_epi64
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2qqs.round.256(<4 x double>
- return _mm256_cvtts_roundpd_epi64(A,_MM_FROUND_NEARBYINT );
-}
-
-__m256i test_mm256_mask_cvtts_roundpd_epi64(__m256i W,__mmask8 U, __m256d A){
-// CHECK-LABEL: @test_mm256_mask_cvtts_roundpd_epi64
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2qqs.round.256(<4 x double>
- return _mm256_mask_cvtts_roundpd_epi64(W,U,A,_MM_FROUND_NEARBYINT );
-}
-
-__m256i test_mm256_maskz_cvtts_roundpd_epi64(__mmask8 U, __m256d A){
-// CHECK-LABEL: @test_mm256_maskz_cvtts_roundpd_epi64
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2qqs.round.256(<4 x double>
- return _mm256_maskz_cvtts_roundpd_epi64(U,A,_MM_FROUND_NEARBYINT );
-}
-
__m256i test_mm256_cvtts_pd_epu64(__m256d A){
// CHECK-LABEL: @test_mm256_cvtts_pd_epu64
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2uqqs.round.256(<4 x double>
+// CHECK: @llvm.x86.avx10.mask.vcvttpd2uqqs.256(<4 x double>
return _mm256_cvtts_pd_epu64(A);
}
__m256i test_mm256_mask_cvtts_pd_epu64(__m256i W,__mmask8 U, __m256d A){
// CHECK-LABEL: @test_mm256_mask_cvtts_pd_epu64
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2uqqs.round.256(<4 x double>
+// CHECK: @llvm.x86.avx10.mask.vcvttpd2uqqs.256(<4 x double>
return _mm256_mask_cvtts_pd_epu64(W,U, A);
}
__m256i test_mm256_maskz_cvtts_pd_epu64(__mmask8 U, __m256d A){
// CHECK-LABEL: @test_mm256_maskz_cvtts_pd_epu64
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2uqqs.round.256(<4 x double>
+// CHECK: @llvm.x86.avx10.mask.vcvttpd2uqqs.256(<4 x double>
return _mm256_maskz_cvtts_pd_epu64(U, A);
}
-__m256i test_mm256_cvtts_roundpd_epu64(__m256d A){
-// CHECK-LABEL: @test_mm256_cvtts_roundpd_epu64
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2uqqs.round.256(<4 x double>
- return _mm256_cvtts_roundpd_epu64(A,_MM_FROUND_NEARBYINT );
-}
-
-__m256i test_mm256_mask_cvtts_roundpd_epu64(__m256i W,__mmask8 U, __m256d A){
-// CHECK-LABEL: @test_mm256_mask_cvtts_roundpd_epu64
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2uqqs.round.256(<4 x double>
- return _mm256_mask_cvtts_roundpd_epu64(W,U,A,_MM_FROUND_NEARBYINT );
-}
-
-__m256i test_mm256_maskz_cvtts_roundpd_epu64(__mmask8 U, __m256d A){
-// CHECK-LABEL: @test_mm256_maskz_cvtts_roundpd_epu64
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2uqqs.round.256(<4 x double>
- return _mm256_maskz_cvtts_roundpd_epu64(U,A,_MM_FROUND_NEARBYINT );
-}
-
// 128 bit
__m128i test_mm_cvtts_ps_epi64(__m128 A){
// CHECK-LABEL: @test_mm_cvtts_ps_epi64
@@ -191,72 +155,36 @@ __m128i test_mm_maskz_cvtts_ps_epu64(__mmask8 U,__m128 A){
__m256i test_mm256_cvtts_ps_epi64(__m128 A){
// CHECK-LABEL: @test_mm256_cvtts_ps_epi64
-// CHECK: @llvm.x86.avx10.mask.vcvttps2qqs.round.256(<4 x float>
+// CHECK: @llvm.x86.avx10.mask.vcvttps2qqs.256(<4 x float>
return _mm256_cvtts_ps_epi64(A);
}
__m256i test_mm256_mask_cvtts_ps_epi64(__m256i W,__mmask8 U, __m128 A){
// CHECK-LABEL: @test_mm256_mask_cvtts_ps_epi64
-// CHECK: @llvm.x86.avx10.mask.vcvttps2qqs.round.256(<4 x float>
+// CHECK: @llvm.x86.avx10.mask.vcvttps2qqs.256(<4 x float>
return _mm256_mask_cvtts_ps_epi64(W,U, A);
}
__m256i test_mm256_maskz_cvtts_ps_epi64(__mmask8 U, __m128 A){
// CHECK-LABEL: @test_mm256_maskz_cvtts_ps_epi64
-// CHECK: @llvm.x86.avx10.mask.vcvttps2qqs.round.256(<4 x float>
+// CHECK: @llvm.x86.avx10.mask.vcvttps2qqs.256(<4 x float>
return _mm256_maskz_cvtts_ps_epi64(U, A);
}
-__m256i test_mm256_cvtts_roundps_epi64(__m128 A){
-// CHECK-LABEL: @test_mm256_cvtts_roundps_epi64
-// CHECK: @llvm.x86.avx10.mask.vcvttps2qqs.round.256(<4 x float>
- return _mm256_cvtts_roundps_epi64(A, _MM_FROUND_NEARBYINT );
-}
-
-__m256i test_mm256_mask_cvtts_roundps_epi64(__m256i W,__mmask8 U, __m128 A){
-// CHECK-LABEL: @test_mm256_mask_cvtts_roundps_epi64
-// CHECK: @llvm.x86.avx10.mask.vcvttps2qqs.round.256(<4 x float>
- return _mm256_mask_cvtts_roundps_epi64(W,U,A,_MM_FROUND_NEARBYINT );
-}
-
-__m256i test_mm256_maskz_cvtts_roundps_epi64(__mmask8 U, __m128 A){
-// CHECK-LABEL: @test_mm256_maskz_cvtts_roundps_epi64
-// CHECK: @llvm.x86.avx10.mask.vcvttps2qqs.round.256(<4 x float>
- return _mm256_maskz_cvtts_roundps_epi64(U,A,_MM_FROUND_NEARBYINT );
-}
-
__m256i test_mm256_cvtts_ps_epu64(__m128 A){
// CHECK-LABEL: @test_mm256_cvtts_ps_epu64
-// CHECK: @llvm.x86.avx10.mask.vcvttps2uqqs.round.256(<4 x float>
+// CHECK: @llvm.x86.avx10.mask.vcvttps2uqqs.256(<4 x float>
return _mm256_cvtts_ps_epu64(A);
}
__m256i test_mm256_mask_cvtts_ps_epu64(__m256i W,__mmask8 U, __m128 A){
// CHECK-LABEL: @test_mm256_mask_cvtts_ps_epu64
-// CHECK: @llvm.x86.avx10.mask.vcvttps2uqqs.round.256(<4 x float>
+// CHECK: @llvm.x86.avx10.mask.vcvttps2uqqs.256(<4 x float>
return _mm256_mask_cvtts_ps_epu64(W,U, A);
}
__m256i test_mm256_maskz_cvtts_ps_epu64(__mmask8 U, __m128 A){
// CHECK-LABEL: @test_mm256_maskz_cvtts_ps_epu64
-// CHECK: @llvm.x86.avx10.mask.vcvttps2uqqs.round.256(<4 x float>
+// CHECK: @llvm.x86.avx10.mask.vcvttps2uqqs.256(<4 x float>
return _mm256_maskz_cvtts_ps_epu64(U, A);
}
-
-__m256i test_mm256_cvtts_roundps_epu64(__m128 A){
-// CHECK-LABEL: @test_mm256_cvtts_roundps_epu64
-// CHECK: @llvm.x86.avx10.mask.vcvttps2uqqs.round.256(<4 x float>
- return _mm256_cvtts_roundps_epu64(A, _MM_FROUND_NEARBYINT );
-}
-
-__m256i test_mm256_mask_cvtts_roundps_epu64(__m256i W,__mmask8 U, __m128 A){
-// CHECK-LABEL: @test_mm256_mask_cvtts_roundps_epu64
-// CHECK: @llvm.x86.avx10.mask.vcvttps2uqqs.round.256(<4 x float>
- return _mm256_mask_cvtts_roundps_epu64(W,U,A,_MM_FROUND_NEARBYINT );
-}
-
-__m256i test_mm256_maskz_cvtts_roundps_epu64(__mmask8 U, __m128 A){
-// CHECK-LABEL: @test_mm256_maskz_cvtts_roundps_epu64
-// CHECK: @llvm.x86.avx10.mask.vcvttps2uqqs.round.256(<4 x float>
- return _mm256_maskz_cvtts_roundps_epu64(U,A,_MM_FROUND_NEARBYINT );
-}
diff --git a/clang/test/CodeGen/X86/avx10_2satcvtds-builtins.c b/clang/test/CodeGen/X86/avx10_2satcvtds-builtins.c
index e23a9b8d5cb3c..86e9df44c0669 100644
--- a/clang/test/CodeGen/X86/avx10_2satcvtds-builtins.c
+++ b/clang/test/CodeGen/X86/avx10_2satcvtds-builtins.c
@@ -1,5 +1,5 @@
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i386 -target-feature +avx10.2-256 -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,X86
-// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64 -target-feature +avx10.2-256 -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,X64
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i386 -target-feature +avx10.2-256 -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64 -target-feature +avx10.2-256 -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK
#include <immintrin.h>
#include <stddef.h>
@@ -24,40 +24,22 @@ __m128i test_mm_maskz_cvtts_pd_epi32( __mmask8 U, __m128d A){
__m128i test_mm256_cvtts_pd_epi32(__m256d A){
// CHECK-LABEL: @test_mm256_cvtts_pd_epi32
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2dqs.round.256(<4 x double>
+// CHECK: @llvm.x86.avx10.mask.vcvttpd2dqs.256(<4 x double>
return _mm256_cvtts_pd_epi32(A);
}
__m128i test_mm256_mask_cvtts_pd_epi32(__m128i W,__mmask8 U, __m256d A){
// CHECK-LABEL: @test_mm256_mask_cvtts_pd_epi32
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2dqs.round.256(<4 x double>
+// CHECK: @llvm.x86.avx10.mask.vcvttpd2dqs.256(<4 x double>
return _mm256_mask_cvtts_pd_epi32(W,U,A);
}
__m128i test_mm256_maskz_cvtts_pd_epi32(__mmask8 U, __m256d A){
// CHECK-LABEL: @test_mm256_maskz_cvtts_pd_epi32
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2dqs.round.256(<4 x double>
+// CHECK: @llvm.x86.avx10.mask.vcvttpd2dqs.256(<4 x double>
return _mm256_maskz_cvtts_pd_epi32(U,A);
}
-__m128i test_mm256_cvtts_roundpd_epi32(__m256d A){
-// CHECK-LABEL: @test_mm256_cvtts_roundpd_epi32
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2dqs.round.256(<4 x double>
- return _mm256_cvtts_roundpd_epi32(A, _MM_FROUND_NEARBYINT);
-}
-
-__m128i test_mm256_mask_cvtts_roundpd_epi32(__m128i W,__mmask8 U, __m256d A){
-// CHECK-LABEL: @test_mm256_mask_cvtts_roundpd_epi32
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2dqs.round.256(<4 x double>
- return _mm256_mask_cvtts_roundpd_epi32(W,U,A,_MM_FROUND_NEARBYINT);
-}
-
-__m128i test_mm256_maskz_cvtts_roundpd_epi32(__mmask8 U, __m256d A){
-// CHECK-LABEL: @test_mm256_maskz_cvtts_roundpd_epi32
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2dqs.round.256(<4 x double>
- return _mm256_maskz_cvtts_roundpd_epi32(U,A,_MM_FROUND_NEARBYINT);
-}
-
__m128i test_mm_cvtts_pd_epu32(__m128d A){
// CHECK-LABEL: @test_mm_cvtts_pd_epu32
// CHECK: @llvm.x86.avx10.mask.vcvttpd2udqs.128(<2 x double>
@@ -79,40 +61,22 @@ __m128i test_mm_maskz_cvtts_pd_epu32( __mmask8 U, __m128d A){
__m128i test_mm256_cvtts_pd_epu32(__m256d A){
// CHECK-LABEL: @test_mm256_cvtts_pd_epu32
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2udqs.round.256(<4 x double>
+// CHECK: @llvm.x86.avx10.mask.vcvttpd2udqs.256(<4 x double>
return _mm256_cvtts_pd_epu32(A);
}
__m128i test_mm256_mask_cvtts_pd_epu32(__m128i W,__mmask8 U, __m256d A){
// CHECK-LABEL: @test_mm256_mask_cvtts_pd_epu32
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2udqs.round.256(<4 x double>
+// CHECK: @llvm.x86.avx10.mask.vcvttpd2udqs.256(<4 x double>
return _mm256_mask_cvtts_pd_epu32(W,U,A);
}
__m128i test_mm256_maskz_cvtts_pd_epu32(__mmask8 U, __m256d A){
// CHECK-LABEL: @test_mm256_maskz_cvtts_pd_epu32
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2udqs.round.256(<4 x double>
+// CHECK: @llvm.x86.avx10.mask.vcvttpd2udqs.256(<4 x double>
return _mm256_maskz_cvtts_pd_epu32(U,A);
}
-__m128i test_mm256_cvtts_roundpd_epu32(__m256d A){
-// CHECK-LABEL: @test_mm256_cvtts_roundpd_epu32
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2udqs.round.256(<4 x double>
- return _mm256_cvtts_roundpd_epu32(A, _MM_FROUND_NEARBYINT);
-}
-
-__m128i test_mm256_mask_cvtts_roundpd_epu32(__m128i W,__mmask8 U, __m256d A){
-// CHECK-LABEL: @test_mm256_mask_cvtts_roundpd_epu32
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2udqs.round.256(<4 x double>
- return _mm256_mask_cvtts_roundpd_epu32(W,U,A,_MM_FROUND_NEARBYINT);
-}
-
-__m128i test_mm256_maskz_cvtts_roundpd_epu32(__mmask8 U, __m256d A){
-// CHECK-LABEL: @test_mm256_maskz_cvtts_roundpd_epu32
-// CHECK: @llvm.x86.avx10.mask.vcvttpd2udqs.round.256(<4 x double>
- return _mm256_maskz_cvtts_roundpd_epu32(U,A,_MM_FROUND_NEARBYINT);
-}
-
__m128i test_mm_cvtts_ps_epi32(__m128 A){
// CHECK-LABEL: @test_mm_cvtts_ps_epi32
// CHECK: @llvm.x86.avx10.mask.vcvttps2dqs.128(<4 x float>
@@ -133,40 +97,22 @@ __m128i test_mm_maskz_cvtts_ps_epi32( __mmask8 U, __m128 A){
__m256i test_mm256_cvtts_ps_epi32(__m256 A){
// CHECK-LABEL: @test_mm256_cvtts_ps_epi32
-// CHECK: @llvm.x86.avx10.mask.vcvttps2dqs.round.256(<8 x float>
+// CHECK: @llvm.x86.avx10.mask.vcvttps2dqs.256(<8 x float>
return _mm256_cvtts_ps_epi32(A);
}
__m256i test_mm256_mask_cvtts_ps_epi32(__m256i W,__mmask8 U, __m256 A){
// CHECK-LABEL: @test_mm256_mask_cvtts_ps_epi32
-// CHECK: @llvm.x86.avx10.mask.vcvttps2dqs.round.256(<8 x float>
+// CHECK: @llvm.x86.avx10.mask.vcvttps2dqs.256(<8 x float>
return _mm256_mask_cvtts_ps_epi32(W,U,A);
}
__m256i test_mm256_maskz_cvtts_ps_epi32(__mmask8 U, __m256 A){
// CHECK-LABEL: @test_mm256_maskz_cvtts_ps_epi32
-// CHECK: @llvm.x86.avx10.mask.vcvttps2dqs.round.256(<8 x float>
+// CHECK: @llvm.x86.avx10.mask.vcvttps2dqs.256(<8 x float>
return _mm256_maskz_cvtts_ps_epi32(U,A);
}
-__m256i test_mm256_cvtts_roundps_epi32(__m256 A){
-// CHECK-LABEL: @test_mm256_cvtts_roundps_epi32
-// CHECK: @llvm.x86.avx10.mask.vcvttps2dqs.round.256(<8 x float>
- return _mm256_cvtts_roundps_epi32(A, _MM_FROUND_NEARBYINT);
-}
-
-__m256i test_mm256_mask_cvtts_roundps_epi32(__m256i W,__mmask8 U, __m256 A){
-// CHECK-LABEL: @test_mm256_mask_cvtts_roundps_epi32
-// CHECK: @llvm.x86.avx10.mask.vcvttps2dqs.round.256(<8 x float>
- return _mm256_mask_cvtts_roundps_epi32(W,U,A,_MM_FROUND_NEARBYINT);
-}
-
-__m256i test_mm256_maskz_cvtts_roundps_epi32(__mmask8 U, __m256 A){
-// CHECK-LABEL: @test_mm256_maskz_cvtts_roundps_epi32
-// CHECK: @llvm.x86.avx10.mask.vcvttps2dqs.round.256(<8 x float>
- return _mm256_maskz_cvtts_roundps_epi32(U,A,_MM_FROUND_NEARBYINT);
-}
-
__m128i test_mm_cvtts_ps_epu32(__m128 A){
// CHECK-LABEL: @test_mm_cvtts_ps_epu32
// CHECK: @llvm.x86.avx10.mask.vcvttps2udqs.128(<4 x float>
@@ -187,39 +133,18 @@ __m128i test_mm_maskz_cvtts_ps_epu32( __mmask8 U, __m128 A){
__m256i test_mm256_cvtts_ps_epu32(__m256 A){
// CHECK-LABEL: @test_mm256_cvtts_ps_epu32
-// CHECK: @llvm.x86.avx10.mask.vcvttps2udqs.round.256(<8 x float>
+// CHECK: @llvm.x86.avx10.mask.vcvttps2udqs.256(<8 x float>
return _mm256_cvtts_ps_epu32(A);
}
__m256i test_mm256_mask_cvtts_ps_epu32(__m256i W,__mmask8 U, __m256 A){
// CHECK-LABEL: @test_mm256_mask_cvtts_ps_epu32
-// CHECK: @llvm.x86.avx10.mask.vcvttps2udqs.round.256(<8 x float>
+// CHECK: @llvm.x86.avx10.mask.vcvttps2udqs.256(<8 x float>
return _mm256_mask_cvtts_ps_epu32(W,U,A);
}
__m256i test_mm256_maskz_cvtts_ps_epu32(__mmask8 U, __m256 A){
// CHECK-LABEL: @test_mm256_maskz_cvtts_ps_epu32
-// CHECK: @llvm.x86.avx10.mask.vcvttps2udqs.round.256(<8 x float>
+// CHECK: @llvm.x86.avx10.mask.vcvttps2udqs.256(<8 x float>
return _mm256_maskz_cvtts_ps_epu32(U,A);
}
-
-__m256i test_mm256_cvtts_roundps_epu32(__m256 A){
-// CHECK-LABEL: @test_mm256_cvtts_roundps_epu32
-// CHECK: @llvm.x86.avx10.mask.vcvttps2udqs.round.256(<8 x float>
- return _mm256_cvtts_roundps_epu32(A, _MM_FROUND_NEARBYINT);
-}
-
-__m256i test_mm256_mask_cvtts_roundps_epu32(__m256i W,__mmask8 U, __m256 A){
-// CHECK-LABEL: @test_mm256_mask_cvtts_roundps_epu32
-// CHECK: @llvm.x86.avx10.mask.vcvttps2udqs.round.256(<8 x float>
- return _mm256_mask_cvtts_roundps_epu32(W,U,A,_MM_FROUND_NEARBYINT);
-}
-
-__m256i test_mm256_maskz_cvtts_roundps_epu32(__mmask8 U, __m256 A){
-// CHECK-LABEL: @test_mm256_maskz_cvtts_roundps_epu32
-// CHECK: @llvm.x86.avx10.mask.vcvttps2udqs.round.256(<8 x float>
- return _mm256_maskz_cvtts_roundps_epu32(U,A,_MM_FROUND_NEARBYINT);
-}
-
-// X64: {{.*}}
-// X86: {{.*}}
diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td
index 4fcf2ff8f38df..9f63d8b75e80a 100644
--- a/llvm/include/llvm/IR/IntrinsicsX86.td
+++ b/llvm/include/llvm/IR/IntrinsicsX86.td
@@ -5113,72 +5113,72 @@ let TargetPrefix = "x86" in {
def int_x86_avx10_mask_vcvttpd2dqs_128 : ClangBuiltin<"__builtin_ia32_vcvttpd2dqs128_mask">,
DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty, llvm_v4i32_ty, llvm_i8_ty],
[IntrNoMem]>;
- def int_x86_avx10_mask_vcvttpd2dqs_round_256: ClangBuiltin<"__builtin_ia32_vcvttpd2dqs256_round_mask">,
- DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4f64_ty, llvm_v4i32_ty, llvm_i8_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ def int_x86_avx10_mask_vcvttpd2dqs_256: ClangBuiltin<"__builtin_ia32_vcvttpd2dqs256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4f64_ty, llvm_v4i32_ty, llvm_i8_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvttpd2dqs_round_512 : ClangBuiltin<"__builtin_ia32_vcvttpd2dqs512_round_mask">,
DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v8f64_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
def int_x86_avx10_mask_vcvttpd2udqs_128 : ClangBuiltin<"__builtin_ia32_vcvttpd2udqs128_mask">,
DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty,llvm_v4i32_ty, llvm_i8_ty],
[IntrNoMem]>;
- def int_x86_avx10_mask_vcvttpd2udqs_round_256: ClangBuiltin<"__builtin_ia32_vcvttpd2udqs256_round_mask">,
- DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4f64_ty, llvm_v4i32_ty, llvm_i8_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ def int_x86_avx10_mask_vcvttpd2udqs_256: ClangBuiltin<"__builtin_ia32_vcvttpd2udqs256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4f64_ty, llvm_v4i32_ty, llvm_i8_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvttpd2udqs_round_512 : ClangBuiltin<"__builtin_ia32_vcvttpd2udqs512_round_mask">,
DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v8f64_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
def int_x86_avx10_mask_vcvttpd2qqs_128 : ClangBuiltin<"__builtin_ia32_vcvttpd2qqs128_mask">,
DefaultAttrsIntrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty,llvm_v2i64_ty, llvm_i8_ty],
[IntrNoMem]>;
- def int_x86_avx10_mask_vcvttpd2qqs_round_256: ClangBuiltin<"__builtin_ia32_vcvttpd2qqs256_round_mask">,
- DefaultAttrsIntrinsic<[llvm_v4i64_ty], [llvm_v4f64_ty, llvm_v4i64_ty, llvm_i8_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ def int_x86_avx10_mask_vcvttpd2qqs_256: ClangBuiltin<"__builtin_ia32_vcvttpd2qqs256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v4i64_ty], [llvm_v4f64_ty, llvm_v4i64_ty, llvm_i8_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvttpd2qqs_round_512 : ClangBuiltin<"__builtin_ia32_vcvttpd2qqs512_round_mask">,
DefaultAttrsIntrinsic<[llvm_v8i64_ty], [llvm_v8f64_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
def int_x86_avx10_mask_vcvttpd2uqqs_128 : ClangBuiltin<"__builtin_ia32_vcvttpd2uqqs128_mask">,
DefaultAttrsIntrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty,llvm_v2i64_ty, llvm_i8_ty],
[IntrNoMem]>;
- def int_x86_avx10_mask_vcvttpd2uqqs_round_256: ClangBuiltin<"__builtin_ia32_vcvttpd2uqqs256_round_mask">,
- DefaultAttrsIntrinsic<[llvm_v4i64_ty], [llvm_v4f64_ty, llvm_v4i64_ty, llvm_i8_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ def int_x86_avx10_mask_vcvttpd2uqqs_256: ClangBuiltin<"__builtin_ia32_vcvttpd2uqqs256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v4i64_ty], [llvm_v4f64_ty, llvm_v4i64_ty, llvm_i8_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvttpd2uqqs_round_512 : ClangBuiltin<"__builtin_ia32_vcvttpd2uqqs512_round_mask">,
DefaultAttrsIntrinsic<[llvm_v8i64_ty], [llvm_v8f64_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
def int_x86_avx10_mask_vcvttps2dqs_128 : ClangBuiltin<"__builtin_ia32_vcvttps2dqs128_mask">,
DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4i32_ty, llvm_i8_ty],
[IntrNoMem]>;
- def int_x86_avx10_mask_vcvttps2dqs_round_256: ClangBuiltin<"__builtin_ia32_vcvttps2dqs256_round_mask">,
- DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ def int_x86_avx10_mask_vcvttps2dqs_256: ClangBuiltin<"__builtin_ia32_vcvttps2dqs256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvttps2dqs_round_512 : ClangBuiltin<"__builtin_ia32_vcvttps2dqs512_round_mask">,
DefaultAttrsIntrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
def int_x86_avx10_mask_vcvttps2udqs_128 : ClangBuiltin<"__builtin_ia32_vcvttps2udqs128_mask">,
DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4i32_ty, llvm_i8_ty],
[IntrNoMem]>;
- def int_x86_avx10_mask_vcvttps2udqs_round_256: ClangBuiltin<"__builtin_ia32_vcvttps2udqs256_round_mask">,
- DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ def int_x86_avx10_mask_vcvttps2udqs_256: ClangBuiltin<"__builtin_ia32_vcvttps2udqs256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty, llvm_v8i32_ty, llvm_i8_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvttps2udqs_round_512 : ClangBuiltin<"__builtin_ia32_vcvttps2udqs512_round_mask">,
DefaultAttrsIntrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty, llvm_v16i32_ty, llvm_i16_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
def int_x86_avx10_mask_vcvttps2qqs_128 : ClangBuiltin<"__builtin_ia32_vcvttps2qqs128_mask">,
DefaultAttrsIntrinsic<[llvm_v2i64_ty], [llvm_v4f32_ty, llvm_v2i64_ty, llvm_i8_ty],
[IntrNoMem]>;
- def int_x86_avx10_mask_vcvttps2qqs_round_256: ClangBuiltin<"__builtin_ia32_vcvttps2qqs256_round_mask">,
- DefaultAttrsIntrinsic<[llvm_v4i64_ty], [llvm_v4f32_ty, llvm_v4i64_ty, llvm_i8_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ def int_x86_avx10_mask_vcvttps2qqs_256: ClangBuiltin<"__builtin_ia32_vcvttps2qqs256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v4i64_ty], [llvm_v4f32_ty, llvm_v4i64_ty, llvm_i8_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvttps2qqs_round_512 : ClangBuiltin<"__builtin_ia32_vcvttps2qqs512_round_mask">,
DefaultAttrsIntrinsic<[llvm_v8i64_ty], [llvm_v8f32_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
def int_x86_avx10_mask_vcvttps2uqqs_128 : ClangBuiltin<"__builtin_ia32_vcvttps2uqqs128_mask">,
DefaultAttrsIntrinsic<[llvm_v2i64_ty], [llvm_v4f32_ty,llvm_v2i64_ty, llvm_i8_ty],
[IntrNoMem]>;
- def int_x86_avx10_mask_vcvttps2uqqs_round_256: ClangBuiltin<"__builtin_ia32_vcvttps2uqqs256_round_mask">,
- DefaultAttrsIntrinsic<[llvm_v4i64_ty], [llvm_v4f32_ty, llvm_v4i64_ty, llvm_i8_ty, llvm_i32_ty],
- [IntrNoMem, ImmArg<ArgIndex<3>>]>;
+ def int_x86_avx10_mask_vcvttps2uqqs_256: ClangBuiltin<"__builtin_ia32_vcvttps2uqqs256_mask">,
+ DefaultAttrsIntrinsic<[llvm_v4i64_ty], [llvm_v4f32_ty, llvm_v4i64_ty, llvm_i8_ty],
+ [IntrNoMem]>;
def int_x86_avx10_mask_vcvttps2uqqs_round_512 : ClangBuiltin<"__builtin_ia32_vcvttps2uqqs512_round_mask">,
DefaultAttrsIntrinsic<[llvm_v8i64_ty], [llvm_v8f32_ty, llvm_v8i64_ty, llvm_i8_ty, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<3>>]>;
diff --git a/llvm/lib/Target/X86/X86InstrAVX10.td b/llvm/lib/Target/X86/X86InstrAVX10.td
index b368a5299f907..a7558ab58746f 100644
--- a/llvm/lib/Target/X86/X86InstrAVX10.td
+++ b/llvm/lib/Target/X86/X86InstrAVX10.td
@@ -501,11 +501,6 @@ multiclass avx10_cvttps2dqs<bits<8> opc, string OpcodeStr, SDPatternOperator OpN
defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode,
MaskOpNode, sched.YMM>, EVEX_V256;
}
-
- let Predicates = [HasAVX10_2], hasEVEX_U=1 in {
- defm Z256 : avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f32x_info,
- OpNodeSAE, sched.YMM>, EVEX_V256;
- }
}
defm VCVTTPD2DQS : avx10_cvttpd2dqs<0x6D, "vcvttpd2dqs", X86cvttp2sis,
diff --git a/llvm/lib/Target/X86/X86IntrinsicsInfo.h b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
index 31c2bfb8f71c2..47684cc2801a8 100644
--- a/llvm/lib/Target/X86/X86IntrinsicsInfo.h
+++ b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
@@ -523,26 +523,26 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86ISD::CVTP2IUBS, X86ISD::CVTP2IUBS_RND),
X86_INTRINSIC_DATA(avx10_mask_vcvttpd2dqs_128, CVTPD2DQ_MASK,
X86ISD::CVTTP2SIS, X86ISD::MCVTTP2SIS),
- X86_INTRINSIC_DATA(avx10_mask_vcvttpd2dqs_round_256, INTR_TYPE_1OP_MASK,
- X86ISD::CVTTP2SIS, X86ISD::CVTTP2SIS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttpd2dqs_256, INTR_TYPE_1OP_MASK,
+ X86ISD::CVTTP2SIS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvttpd2dqs_round_512, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2SIS, X86ISD::CVTTP2SIS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vcvttpd2qqs_128, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2SIS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvttpd2qqs_round_256, INTR_TYPE_1OP_MASK,
- X86ISD::CVTTP2SIS, X86ISD::CVTTP2SIS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttpd2qqs_256, INTR_TYPE_1OP_MASK,
+ X86ISD::CVTTP2SIS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvttpd2qqs_round_512, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2SIS, X86ISD::CVTTP2SIS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vcvttpd2udqs_128, CVTPD2DQ_MASK,
X86ISD::CVTTP2UIS, X86ISD::MCVTTP2SIS),
- X86_INTRINSIC_DATA(avx10_mask_vcvttpd2udqs_round_256, INTR_TYPE_1OP_MASK,
- X86ISD::CVTTP2UIS, X86ISD::CVTTP2UIS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttpd2udqs_256, INTR_TYPE_1OP_MASK,
+ X86ISD::CVTTP2UIS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvttpd2udqs_round_512, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2UIS, X86ISD::CVTTP2UIS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vcvttpd2uqqs_128, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2UIS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvttpd2uqqs_round_256, INTR_TYPE_1OP_MASK,
- X86ISD::CVTTP2UIS, X86ISD::CVTTP2UIS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttpd2uqqs_256, INTR_TYPE_1OP_MASK,
+ X86ISD::CVTTP2UIS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvttpd2uqqs_round_512, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2UIS, X86ISD::CVTTP2UIS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vcvttph2ibs128, INTR_TYPE_1OP_MASK,
@@ -559,8 +559,8 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86ISD::CVTTP2IUBS, X86ISD::CVTTP2IUBS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vcvttps2dqs_128, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2SIS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvttps2dqs_round_256, INTR_TYPE_1OP_MASK,
- X86ISD::CVTTP2SIS, X86ISD::CVTTP2SIS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttps2dqs_256, INTR_TYPE_1OP_MASK,
+ X86ISD::CVTTP2SIS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvttps2dqs_round_512, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2SIS, X86ISD::CVTTP2SIS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vcvttps2ibs128, INTR_TYPE_1OP_MASK,
@@ -577,20 +577,20 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86ISD::CVTTP2IUBS, X86ISD::CVTTP2IUBS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vcvttps2qqs_128, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2SIS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvttps2qqs_round_256, INTR_TYPE_1OP_MASK,
- X86ISD::CVTTP2SIS, X86ISD::CVTTP2SIS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttps2qqs_256, INTR_TYPE_1OP_MASK,
+ X86ISD::CVTTP2SIS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvttps2qqs_round_512, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2SIS, X86ISD::CVTTP2SIS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vcvttps2udqs_128, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2UIS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvttps2udqs_round_256, INTR_TYPE_1OP_MASK,
- X86ISD::CVTTP2UIS, X86ISD::CVTTP2UIS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttps2udqs_256, INTR_TYPE_1OP_MASK,
+ X86ISD::CVTTP2UIS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvttps2udqs_round_512, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2UIS, X86ISD::CVTTP2UIS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vcvttps2uqqs_128, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2UIS, 0),
- X86_INTRINSIC_DATA(avx10_mask_vcvttps2uqqs_round_256, INTR_TYPE_1OP_MASK,
- X86ISD::CVTTP2UIS, X86ISD::CVTTP2UIS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vcvttps2uqqs_256, INTR_TYPE_1OP_MASK,
+ X86ISD::CVTTP2UIS, 0),
X86_INTRINSIC_DATA(avx10_mask_vcvttps2uqqs_round_512, INTR_TYPE_1OP_MASK,
X86ISD::CVTTP2UIS, X86ISD::CVTTP2UIS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vminmaxpd_round, INTR_TYPE_3OP_MASK_SAE,
diff --git a/llvm/test/CodeGen/X86/avx10_2satcvtds-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2satcvtds-intrinsics.ll
index 922ac92be174a..e9b739074b453 100644
--- a/llvm/test/CodeGen/X86/avx10_2satcvtds-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/avx10_2satcvtds-intrinsics.ll
@@ -90,7 +90,7 @@ define <4 x i32> @test_int_x86_mask_vcvtt_pd2dqs_256(<4 x double> %x0, <4 x i32>
; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2dqs.round.256( <4 x double> %x0, <4 x i32> %src, i8 %mask, i32 4)
+ %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2dqs.256( <4 x double> %x0, <4 x i32> %src, i8 %mask)
ret <4 x i32> %res
}
@@ -108,7 +108,7 @@ define <4 x i32> @test_int_x86_maskz_vcvtt_pd2dqs_256_z(<4 x double> %x0, i8 %ma
; X86-NEXT: vcvttpd2dqs %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0xfc,0xa9,0x6d,0xc0]
; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2dqs.round.256( <4 x double> %x0, <4 x i32> zeroinitializer, i8 %mask, i32 4)
+ %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2dqs.256( <4 x double> %x0, <4 x i32> zeroinitializer, i8 %mask)
ret <4 x i32> %res
}
@@ -126,7 +126,7 @@ define <4 x i32> @test_int_x86_mask_vcvtt_pd2dqs_256_undef(<4 x double> %x0, i8
; X86-NEXT: vcvttpd2dqs %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0xfc,0xa9,0x6d,0xc0]
; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2dqs.round.256( <4 x double> %x0, <4 x i32> undef, i8 %mask, i32 4)
+ %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2dqs.256( <4 x double> %x0, <4 x i32> undef, i8 %mask)
ret <4 x i32> %res
}
@@ -142,10 +142,10 @@ define <4 x i32> @test_int_x86_mask_vcvtt_pd2dqs_256_default(<4 x double>* %xptr
; X86-NEXT: vcvttpd2dqsy (%eax), %xmm0 # encoding: [0x62,0xf5,0xfc,0x28,0x6d,0x00]
; X86-NEXT: retl # encoding: [0xc3]
%x0 = load <4 x double>, <4 x double> * %xptr
- %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2dqs.round.256( <4 x double> %x0, <4 x i32> undef, i8 -1, i32 4)
+ %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2dqs.256( <4 x double> %x0, <4 x i32> undef, i8 -1)
ret <4 x i32> %res
}
-declare <4 x i32> @llvm.x86.avx10.mask.vcvttpd2dqs.round.256(<4 x double>, <4 x i32>, i8 , i32)
+declare <4 x i32> @llvm.x86.avx10.mask.vcvttpd2dqs.256(<4 x double>, <4 x i32>, i8 )
define <4 x i32> @test_int_x86_mask_vcvtt_pd2udqs_256(<4 x double> %x0, <4 x i32> %src, i8 %mask) {
; X64-LABEL: test_int_x86_mask_vcvtt_pd2udqs_256:
@@ -163,7 +163,7 @@ define <4 x i32> @test_int_x86_mask_vcvtt_pd2udqs_256(<4 x double> %x0, <4 x i32
; X86-NEXT: vmovaps %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc1]
; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2udqs.round.256( <4 x double> %x0, <4 x i32> %src, i8 %mask, i32 4)
+ %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2udqs.256( <4 x double> %x0, <4 x i32> %src, i8 %mask)
ret <4 x i32> %res
}
@@ -181,7 +181,7 @@ define <4 x i32> @test_int_x86_maskz_vcvtt_pd2udqs_256_z(<4 x double> %x0, i8 %m
; X86-NEXT: vcvttpd2udqs %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0xfc,0xa9,0x6c,0xc0]
; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2udqs.round.256( <4 x double> %x0, <4 x i32> zeroinitializer, i8 %mask, i32 4)
+ %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2udqs.256( <4 x double> %x0, <4 x i32> zeroinitializer, i8 %mask)
ret <4 x i32> %res
}
@@ -199,7 +199,7 @@ define <4 x i32> @test_int_x86_mask_vcvtt_pd2udqs_256_undef(<4 x double> %x0, i8
; X86-NEXT: vcvttpd2udqs %ymm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0xfc,0xa9,0x6c,0xc0]
; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2udqs.round.256( <4 x double> %x0, <4 x i32> undef, i8 %mask, i32 4)
+ %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2udqs.256( <4 x double> %x0, <4 x i32> undef, i8 %mask)
ret <4 x i32> %res
}
@@ -216,10 +216,10 @@ define <4 x i32> @test_int_x86_mask_vcvtt_pd2udqs_256_default(<4 x double>* %x0)
; X86-NEXT: vcvttpd2udqsy (%eax), %xmm0 # encoding: [0x62,0xf5,0xfc,0x28,0x6c,0x00]
; X86-NEXT: retl # encoding: [0xc3]
%x10 = load <4 x double>, <4 x double> * %x0
- %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2udqs.round.256( <4 x double> %x10, <4 x i32> undef, i8 -1, i32 4)
+ %res = call <4 x i32> @llvm.x86.avx10.mask.vcvttpd2udqs.256( <4 x double> %x10, <4 x i32> undef, i8 -1)
ret <4 x i32> %res
}
-declare <4 x i32> @llvm.x86.avx10.mask.vcvttpd2udqs.round.256(<4 x double>, <4 x i32>, i8 , i32)
+declare <4 x i32> @llvm.x86.avx10.mask.vcvttpd2udqs.256(<4 x double>, <4 x i32>, i8 )
define <4 x i64> @test_int_x86_mask_vcvtt_pd2qqs_256(<4 x double> %x0, <4 x i64> %src, i8 %mask) {
; X64-LABEL: test_int_x86_mask_vcvtt_pd2qqs_256:
@@ -235,7 +235,7 @@ define <4 x i64> @test_int_x86_mask_vcvtt_pd2qqs_256(<4 x double> %x0, <4 x i64>
; X86-NEXT: vcvttpd2qqs %ymm0, %ymm1 {%k1} # encoding: [0x62,0xf5,0xfd,0x29,0x6d,0xc8]
; X86-NEXT: vmovaps %ymm1, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xc1]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2qqs.round.256( <4 x double> %x0, <4 x i64> %src, i8 %mask, i32 4)
+ %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2qqs.256( <4 x double> %x0, <4 x i64> %src, i8 %mask)
ret <4 x i64> %res
}
@@ -251,7 +251,7 @@ define <4 x i64> @test_int_x86_maskz_vcvtt_pd2qqs_256_z(<4 x double> %x0, i8 %ma
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvttpd2qqs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0xfd,0xa9,0x6d,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2qqs.round.256( <4 x double> %x0, <4 x i64> zeroinitializer, i8 %mask, i32 4)
+ %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2qqs.256( <4 x double> %x0, <4 x i64> zeroinitializer, i8 %mask)
ret <4 x i64> %res
}
@@ -267,7 +267,7 @@ define <4 x i64> @test_int_x86_mask_vcvtt_pd2qqs_256_undef(<4 x double> %x0, i8
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvttpd2qqs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0xfd,0xa9,0x6d,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2qqs.round.256( <4 x double> %x0, <4 x i64> undef, i8 %mask, i32 4)
+ %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2qqs.256( <4 x double> %x0, <4 x i64> undef, i8 %mask)
ret <4 x i64> %res
}
@@ -284,10 +284,10 @@ define <4 x i64> @test_int_x86_mask_vcvtt_pd2qqs_256_default(<4 x double>* %x0)
; X86-NEXT: vcvttpd2qqs (%eax), %ymm0 # encoding: [0x62,0xf5,0xfd,0x28,0x6d,0x00]
; X86-NEXT: retl # encoding: [0xc3]
%x10 = load <4 x double>, <4 x double>* %x0
- %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2qqs.round.256( <4 x double> %x10, <4 x i64> undef, i8 -1, i32 4)
+ %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2qqs.256( <4 x double> %x10, <4 x i64> undef, i8 -1)
ret <4 x i64> %res
}
-declare <4 x i64> @llvm.x86.avx10.mask.vcvttpd2qqs.round.256(<4 x double>, <4 x i64>, i8 , i32)
+declare <4 x i64> @llvm.x86.avx10.mask.vcvttpd2qqs.256(<4 x double>, <4 x i64>, i8 )
define <4 x i64> @test_int_x86_mask_vcvtt_pd2uqqs_256(<4 x double> %x0, <4 x i64> %src, i8 %mask) {
; X64-LABEL: test_int_x86_mask_vcvtt_pd2uqqs_256:
@@ -303,7 +303,7 @@ define <4 x i64> @test_int_x86_mask_vcvtt_pd2uqqs_256(<4 x double> %x0, <4 x i64
; X86-NEXT: vcvttpd2uqqs %ymm0, %ymm1 {%k1} # encoding: [0x62,0xf5,0xfd,0x29,0x6c,0xc8]
; X86-NEXT: vmovaps %ymm1, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xc1]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2uqqs.round.256( <4 x double> %x0, <4 x i64> %src, i8 %mask, i32 4)
+ %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2uqqs.256( <4 x double> %x0, <4 x i64> %src, i8 %mask)
ret <4 x i64> %res
}
@@ -319,7 +319,7 @@ define <4 x i64> @test_int_x86_maskz_vcvtt_pd2uqqs_256_z(<4 x double> %x0, i8 %m
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvttpd2uqqs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0xfd,0xa9,0x6c,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2uqqs.round.256( <4 x double> %x0, <4 x i64> zeroinitializer, i8 %mask, i32 4)
+ %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2uqqs.256( <4 x double> %x0, <4 x i64> zeroinitializer, i8 %mask)
ret <4 x i64> %res
}
@@ -335,7 +335,7 @@ define <4 x i64> @test_int_x86_mask_vcvtt_pd2uqqs_256_undef(<4 x double> %x0, i8
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvttpd2uqqs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0xfd,0xa9,0x6c,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2uqqs.round.256( <4 x double> %x0, <4 x i64> undef, i8 %mask, i32 4)
+ %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2uqqs.256( <4 x double> %x0, <4 x i64> undef, i8 %mask)
ret <4 x i64> %res
}
@@ -352,10 +352,10 @@ define <4 x i64> @test_int_x86_mask_vcvtt_pd2uqqs_256_default(<4 x double>* %x0)
; X86-NEXT: vcvttpd2uqqs (%eax), %ymm0 # encoding: [0x62,0xf5,0xfd,0x28,0x6c,0x00]
; X86-NEXT: retl # encoding: [0xc3]
%x10 = load <4 x double>, <4 x double>* %x0
- %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2uqqs.round.256( <4 x double> %x10, <4 x i64> undef, i8 -1, i32 4)
+ %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttpd2uqqs.256( <4 x double> %x10, <4 x i64> undef, i8 -1)
ret <4 x i64> %res
}
-declare <4 x i64> @llvm.x86.avx10.mask.vcvttpd2uqqs.round.256(<4 x double>, <4 x i64>, i8 , i32)
+declare <4 x i64> @llvm.x86.avx10.mask.vcvttpd2uqqs.256(<4 x double>, <4 x i64>, i8 )
define <8 x i32> @test_int_x86_mask_vcvtt_ps2dqs_256(<8 x float> %x0, <8 x i32> %src, i8 %mask) {
; X64-LABEL: test_int_x86_mask_vcvtt_ps2dqs_256:
@@ -371,7 +371,7 @@ define <8 x i32> @test_int_x86_mask_vcvtt_ps2dqs_256(<8 x float> %x0, <8 x i32>
; X86-NEXT: vcvttps2dqs %ymm0, %ymm1 {%k1} # encoding: [0x62,0xf5,0x7c,0x29,0x6d,0xc8]
; X86-NEXT: vmovaps %ymm1, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xc1]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2dqs.round.256( <8 x float> %x0, <8 x i32> %src, i8 %mask, i32 4)
+ %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2dqs.256( <8 x float> %x0, <8 x i32> %src, i8 %mask)
ret <8 x i32> %res
}
@@ -387,7 +387,7 @@ define <8 x i32> @test_int_x86_maskz_vcvtt_ps2dqs_256_z(<8 x float> %x0, i8 %mas
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvttps2dqs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x6d,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2dqs.round.256( <8 x float> %x0, <8 x i32> zeroinitializer, i8 %mask, i32 4)
+ %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2dqs.256( <8 x float> %x0, <8 x i32> zeroinitializer, i8 %mask)
ret <8 x i32> %res
}
@@ -403,7 +403,7 @@ define <8 x i32> @test_int_x86_mask_vcvtt_ps2dqs_256_undef(<8 x float> %x0, i8 %
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvttps2dqs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x6d,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2dqs.round.256( <8 x float> %x0, <8 x i32> undef, i8 %mask, i32 4)
+ %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2dqs.256( <8 x float> %x0, <8 x i32> undef, i8 %mask)
ret <8 x i32> %res
}
@@ -419,10 +419,10 @@ define <8 x i32> @test_int_x86_mask_vcvtt_ps2dqs_256_default(<8 x float>* %x0) {
; X86-NEXT: vcvttps2dqs (%eax), %ymm0 # encoding: [0x62,0xf5,0x7c,0x28,0x6d,0x00]
; X86-NEXT: retl # encoding: [0xc3]
%x10 = load <8 x float>, <8 x float>* %x0
- %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2dqs.round.256( <8 x float> %x10, <8 x i32> undef, i8 -1, i32 4)
+ %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2dqs.256( <8 x float> %x10, <8 x i32> undef, i8 -1)
ret <8 x i32> %res
}
-declare <8 x i32> @llvm.x86.avx10.mask.vcvttps2dqs.round.256(<8 x float>, <8 x i32>, i8 , i32)
+declare <8 x i32> @llvm.x86.avx10.mask.vcvttps2dqs.256(<8 x float>, <8 x i32>, i8 )
define <8 x i32> @test_int_x86_mask_vcvtt_ps2udqs_256(<8 x float> %x0, <8 x i32> %src, i8 %mask) {
; X64-LABEL: test_int_x86_mask_vcvtt_ps2udqs_256:
@@ -438,7 +438,7 @@ define <8 x i32> @test_int_x86_mask_vcvtt_ps2udqs_256(<8 x float> %x0, <8 x i32>
; X86-NEXT: vcvttps2udqs %ymm0, %ymm1 {%k1} # encoding: [0x62,0xf5,0x7c,0x29,0x6c,0xc8]
; X86-NEXT: vmovaps %ymm1, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xc1]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2udqs.round.256( <8 x float> %x0, <8 x i32> %src, i8 %mask, i32 4)
+ %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2udqs.256( <8 x float> %x0, <8 x i32> %src, i8 %mask)
ret <8 x i32> %res
}
@@ -454,7 +454,7 @@ define <8 x i32> @test_int_x86_maskz_vcvtt_ps2udqs_256_z(<8 x float> %x0, i8 %ma
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvttps2udqs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x6c,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2udqs.round.256( <8 x float> %x0, <8 x i32> zeroinitializer, i8 %mask, i32 4)
+ %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2udqs.256( <8 x float> %x0, <8 x i32> zeroinitializer, i8 %mask)
ret <8 x i32> %res
}
@@ -470,7 +470,7 @@ define <8 x i32> @test_int_x86_mask_vcvtt_ps2udqs_256_undef(<8 x float> %x0, i8
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvttps2udqs %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7c,0xa9,0x6c,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2udqs.round.256( <8 x float> %x0, <8 x i32> undef, i8 %mask, i32 4)
+ %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2udqs.256( <8 x float> %x0, <8 x i32> undef, i8 %mask)
ret <8 x i32> %res
}
@@ -487,10 +487,10 @@ define <8 x i32> @test_int_x86_mask_vcvtt_ps2udqs_256_default(<8 x float>* %x0)
; X86-NEXT: vcvttps2udqs (%eax), %ymm0 # encoding: [0x62,0xf5,0x7c,0x28,0x6c,0x00]
; X86-NEXT: retl # encoding: [0xc3]
%x10 = load <8 x float>, <8 x float>* %x0
- %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2udqs.round.256( <8 x float> %x10, <8 x i32> undef, i8 -1, i32 4)
+ %res = call <8 x i32> @llvm.x86.avx10.mask.vcvttps2udqs.256( <8 x float> %x10, <8 x i32> undef, i8 -1)
ret <8 x i32> %res
}
-declare <8 x i32> @llvm.x86.avx10.mask.vcvttps2udqs.round.256(<8 x float>, <8 x i32>, i8 , i32)
+declare <8 x i32> @llvm.x86.avx10.mask.vcvttps2udqs.256(<8 x float>, <8 x i32>, i8 )
define <4 x i64> @test_int_x86_maskz_vcvtt_ps2qqs_256_z(<4 x float> %x0, i8 %mask) {
; X64-LABEL: test_int_x86_maskz_vcvtt_ps2qqs_256_z:
@@ -504,7 +504,7 @@ define <4 x i64> @test_int_x86_maskz_vcvtt_ps2qqs_256_z(<4 x float> %x0, i8 %mas
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvttps2qqs %xmm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xa9,0x6d,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttps2qqs.round.256( <4 x float> %x0, <4 x i64> zeroinitializer, i8 %mask, i32 4)
+ %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttps2qqs.256( <4 x float> %x0, <4 x i64> zeroinitializer, i8 %mask)
ret <4 x i64> %res
}
@@ -520,10 +520,10 @@ define <4 x i64> @test_int_x86_mask_vcvtt_ps2qqs_256_undef(<4 x float> %x0, i8 %
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvttps2qqs %xmm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xa9,0x6d,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttps2qqs.round.256( <4 x float> %x0, <4 x i64> undef, i8 %mask, i32 4)
+ %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttps2qqs.256( <4 x float> %x0, <4 x i64> undef, i8 %mask)
ret <4 x i64> %res
}
-declare <4 x i64> @llvm.x86.avx10.mask.vcvttps2qqs.round.256(<4 x float>, <4 x i64>, i8 , i32)
+declare <4 x i64> @llvm.x86.avx10.mask.vcvttps2qqs.256(<4 x float>, <4 x i64>, i8 )
define <4 x i64> @test_int_x86_mask_vcvtt_ps2uqqs_256(<4 x float> %x0, <4 x i64> %src, i8 %mask) {
; X64-LABEL: test_int_x86_mask_vcvtt_ps2uqqs_256:
@@ -539,7 +539,7 @@ define <4 x i64> @test_int_x86_mask_vcvtt_ps2uqqs_256(<4 x float> %x0, <4 x i64>
; X86-NEXT: vcvttps2uqqs %xmm0, %ymm1 {%k1} # encoding: [0x62,0xf5,0x7d,0x29,0x6c,0xc8]
; X86-NEXT: vmovaps %ymm1, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xc1]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttps2uqqs.round.256( <4 x float> %x0, <4 x i64> %src, i8 %mask, i32 4)
+ %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttps2uqqs.256( <4 x float> %x0, <4 x i64> %src, i8 %mask)
ret <4 x i64> %res
}
@@ -555,7 +555,7 @@ define <4 x i64> @test_int_x86_maskz_vcvtt_ps2uqqs_256_z(<4 x float> %x0, i8 %ma
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvttps2uqqs %xmm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xa9,0x6c,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttps2uqqs.round.256( <4 x float> %x0, <4 x i64> zeroinitializer, i8 %mask, i32 4)
+ %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttps2uqqs.256( <4 x float> %x0, <4 x i64> zeroinitializer, i8 %mask)
ret <4 x i64> %res
}
@@ -571,7 +571,7 @@ define <4 x i64> @test_int_x86_mask_vcvtt_ps2uqqs_256_undef(<4 x float> %x0, i8
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vcvttps2uqqs %xmm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x7d,0xa9,0x6c,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
- %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttps2uqqs.round.256( <4 x float> %x0, <4 x i64> undef, i8 %mask, i32 4)
+ %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttps2uqqs.256( <4 x float> %x0, <4 x i64> undef, i8 %mask)
ret <4 x i64> %res
}
@@ -581,11 +581,11 @@ define <4 x i64> @test_int_x86_mask_vcvtt_ps2uqqs_256_default(<4 x float> %x0) {
; CHECK: # %bb.0:
; CHECK-NEXT: vcvttps2uqqs %xmm0, %ymm0 # encoding: [0x62,0xf5,0x7d,0x28,0x6c,0xc0]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
- %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttps2uqqs.round.256( <4 x float> %x0, <4 x i64> undef, i8 -1, i32 4)
+ %res = call <4 x i64> @llvm.x86.avx10.mask.vcvttps2uqqs.256( <4 x float> %x0, <4 x i64> undef, i8 -1)
ret <4 x i64> %res
}
-declare <4 x i64> @llvm.x86.avx10.mask.vcvttps2uqqs.round.256(<4 x float>, <4 x i64>, i8 , i32)
+declare <4 x i64> @llvm.x86.avx10.mask.vcvttps2uqqs.256(<4 x float>, <4 x i64>, i8 )
define <4 x i32> @test_int_x86_mask_vcvtt_pd2dqs_128(<2 x double> %x0, <4 x i32> %src, i8 %mask) {
; X64-LABEL: test_int_x86_mask_vcvtt_pd2dqs_128:
diff --git a/llvm/test/MC/Disassembler/X86/avx10.2-satcvtds-32.txt b/llvm/test/MC/Disassembler/X86/avx10.2-satcvtds-32.txt
index b2b8267618c18..d2bdd1cb9d543 100644
--- a/llvm/test/MC/Disassembler/X86/avx10.2-satcvtds-32.txt
+++ b/llvm/test/MC/Disassembler/X86/avx10.2-satcvtds-32.txt
@@ -17,18 +17,10 @@
# INTEL: vcvttpd2dqs xmm2, ymm3
0x62,0xf5,0xfc,0x28,0x6d,0xd3
-# ATT: vcvttpd2dqs {sae}, %ymm3, %xmm2
-# INTEL: vcvttpd2dqs xmm2, ymm3, {sae}
-0x62,0xf5,0xf8,0x18,0x6d,0xd3
-
# ATT: vcvttpd2dqs %ymm3, %xmm2 {%k7}
# INTEL: vcvttpd2dqs xmm2 {k7}, ymm3
0x62,0xf5,0xfc,0x2f,0x6d,0xd3
-# ATT: vcvttpd2dqs {sae}, %ymm3, %xmm2 {%k7} {z}
-# INTEL: vcvttpd2dqs xmm2 {k7} {z}, ymm3, {sae}
-0x62,0xf5,0xf8,0x9f,0x6d,0xd3
-
# ATT: vcvttpd2dqs %zmm3, %ymm2
# INTEL: vcvttpd2dqs ymm2, zmm3
0x62,0xf5,0xfc,0x48,0x6d,0xd3
@@ -125,18 +117,10 @@
# INTEL: vcvttpd2qqs ymm2, ymm3
0x62,0xf5,0xfd,0x28,0x6d,0xd3
-# ATT: vcvttpd2qqs {sae}, %ymm3, %ymm2
-# INTEL: vcvttpd2qqs ymm2, ymm3, {sae}
-0x62,0xf5,0xf9,0x18,0x6d,0xd3
-
# ATT: vcvttpd2qqs %ymm3, %ymm2 {%k7}
# INTEL: vcvttpd2qqs ymm2 {k7}, ymm3
0x62,0xf5,0xfd,0x2f,0x6d,0xd3
-# ATT: vcvttpd2qqs {sae}, %ymm3, %ymm2 {%k7} {z}
-# INTEL: vcvttpd2qqs ymm2 {k7} {z}, ymm3, {sae}
-0x62,0xf5,0xf9,0x9f,0x6d,0xd3
-
# ATT: vcvttpd2qqs %zmm3, %zmm2
# INTEL: vcvttpd2qqs zmm2, zmm3
0x62,0xf5,0xfd,0x48,0x6d,0xd3
@@ -241,18 +225,10 @@
# INTEL: vcvttpd2udqs xmm2, ymm3
0x62,0xf5,0xfc,0x28,0x6c,0xd3
-# ATT: vcvttpd2udqs {sae}, %ymm3, %xmm2
-# INTEL: vcvttpd2udqs xmm2, ymm3, {sae}
-0x62,0xf5,0xf8,0x18,0x6c,0xd3
-
# ATT: vcvttpd2udqs %ymm3, %xmm2 {%k7}
# INTEL: vcvttpd2udqs xmm2 {k7}, ymm3
0x62,0xf5,0xfc,0x2f,0x6c,0xd3
-# ATT: vcvttpd2udqs {sae}, %ymm3, %xmm2 {%k7} {z}
-# INTEL: vcvttpd2udqs xmm2 {k7} {z}, ymm3, {sae}
-0x62,0xf5,0xf8,0x9f,0x6c,0xd3
-
# ATT: vcvttpd2udqs %zmm3, %ymm2
# INTEL: vcvttpd2udqs ymm2, zmm3
0x62,0xf5,0xfc,0x48,0x6c,0xd3
@@ -349,18 +325,10 @@
# INTEL: vcvttpd2uqqs ymm2, ymm3
0x62,0xf5,0xfd,0x28,0x6c,0xd3
-# ATT: vcvttpd2uqqs {sae}, %ymm3, %ymm2
-# INTEL: vcvttpd2uqqs ymm2, ymm3, {sae}
-0x62,0xf5,0xf9,0x18,0x6c,0xd3
-
# ATT: vcvttpd2uqqs %ymm3, %ymm2 {%k7}
# INTEL: vcvttpd2uqqs ymm2 {k7}, ymm3
0x62,0xf5,0xfd,0x2f,0x6c,0xd3
-# ATT: vcvttpd2uqqs {sae}, %ymm3, %ymm2 {%k7} {z}
-# INTEL: vcvttpd2uqqs ymm2 {k7} {z}, ymm3, {sae}
-0x62,0xf5,0xf9,0x9f,0x6c,0xd3
-
# ATT: vcvttpd2uqqs %zmm3, %zmm2
# INTEL: vcvttpd2uqqs zmm2, zmm3
0x62,0xf5,0xfd,0x48,0x6c,0xd3
@@ -465,18 +433,10 @@
# INTEL: vcvttps2dqs ymm2, ymm3
0x62,0xf5,0x7c,0x28,0x6d,0xd3
-# ATT: vcvttps2dqs {sae}, %ymm3, %ymm2
-# INTEL: vcvttps2dqs ymm2, ymm3, {sae}
-0x62,0xf5,0x78,0x18,0x6d,0xd3
-
# ATT: vcvttps2dqs %ymm3, %ymm2 {%k7}
# INTEL: vcvttps2dqs ymm2 {k7}, ymm3
0x62,0xf5,0x7c,0x2f,0x6d,0xd3
-# ATT: vcvttps2dqs {sae}, %ymm3, %ymm2 {%k7} {z}
-# INTEL: vcvttps2dqs ymm2 {k7} {z}, ymm3, {sae}
-0x62,0xf5,0x78,0x9f,0x6d,0xd3
-
# ATT: vcvttps2dqs %zmm3, %zmm2
# INTEL: vcvttps2dqs zmm2, zmm3
0x62,0xf5,0x7c,0x48,0x6d,0xd3
@@ -697,18 +657,10 @@
# INTEL: vcvttps2udqs ymm2, ymm3
0x62,0xf5,0x7c,0x28,0x6c,0xd3
-# ATT: vcvttps2udqs {sae}, %ymm3, %ymm2
-# INTEL: vcvttps2udqs ymm2, ymm3, {sae}
-0x62,0xf5,0x78,0x18,0x6c,0xd3
-
# ATT: vcvttps2udqs %ymm3, %ymm2 {%k7}
# INTEL: vcvttps2udqs ymm2 {k7}, ymm3
0x62,0xf5,0x7c,0x2f,0x6c,0xd3
-# ATT: vcvttps2udqs {sae}, %ymm3, %ymm2 {%k7} {z}
-# INTEL: vcvttps2udqs ymm2 {k7} {z}, ymm3, {sae}
-0x62,0xf5,0x78,0x9f,0x6c,0xd3
-
# ATT: vcvttps2udqs %zmm3, %zmm2
# INTEL: vcvttps2udqs zmm2, zmm3
0x62,0xf5,0x7c,0x48,0x6c,0xd3
diff --git a/llvm/test/MC/Disassembler/X86/avx10.2-satcvtds-64.txt b/llvm/test/MC/Disassembler/X86/avx10.2-satcvtds-64.txt
index c0c3340dcc435..23cd7437a7b3c 100644
--- a/llvm/test/MC/Disassembler/X86/avx10.2-satcvtds-64.txt
+++ b/llvm/test/MC/Disassembler/X86/avx10.2-satcvtds-64.txt
@@ -17,18 +17,10 @@
# INTEL: vcvttpd2dqs xmm22, ymm23
0x62,0xa5,0xfc,0x28,0x6d,0xf7
-# ATT: vcvttpd2dqs {sae}, %ymm23, %xmm22
-# INTEL: vcvttpd2dqs xmm22, ymm23, {sae}
-0x62,0xa5,0xf8,0x18,0x6d,0xf7
-
# ATT: vcvttpd2dqs %ymm23, %xmm22 {%k7}
# INTEL: vcvttpd2dqs xmm22 {k7}, ymm23
0x62,0xa5,0xfc,0x2f,0x6d,0xf7
-# ATT: vcvttpd2dqs {sae}, %ymm23, %xmm22 {%k7} {z}
-# INTEL: vcvttpd2dqs xmm22 {k7} {z}, ymm23, {sae}
-0x62,0xa5,0xf8,0x9f,0x6d,0xf7
-
# ATT: vcvttpd2dqs %zmm23, %ymm22
# INTEL: vcvttpd2dqs ymm22, zmm23
0x62,0xa5,0xfc,0x48,0x6d,0xf7
@@ -125,18 +117,10 @@
# INTEL: vcvttpd2qqs ymm22, ymm23
0x62,0xa5,0xfd,0x28,0x6d,0xf7
-# ATT: vcvttpd2qqs {sae}, %ymm23, %ymm22
-# INTEL: vcvttpd2qqs ymm22, ymm23, {sae}
-0x62,0xa5,0xf9,0x18,0x6d,0xf7
-
# ATT: vcvttpd2qqs %ymm23, %ymm22 {%k7}
# INTEL: vcvttpd2qqs ymm22 {k7}, ymm23
0x62,0xa5,0xfd,0x2f,0x6d,0xf7
-# ATT: vcvttpd2qqs {sae}, %ymm23, %ymm22 {%k7} {z}
-# INTEL: vcvttpd2qqs ymm22 {k7} {z}, ymm23, {sae}
-0x62,0xa5,0xf9,0x9f,0x6d,0xf7
-
# ATT: vcvttpd2qqs %zmm23, %zmm22
# INTEL: vcvttpd2qqs zmm22, zmm23
0x62,0xa5,0xfd,0x48,0x6d,0xf7
@@ -241,18 +225,10 @@
# INTEL: vcvttpd2udqs xmm22, ymm23
0x62,0xa5,0xfc,0x28,0x6c,0xf7
-# ATT: vcvttpd2udqs {sae}, %ymm23, %xmm22
-# INTEL: vcvttpd2udqs xmm22, ymm23, {sae}
-0x62,0xa5,0xf8,0x18,0x6c,0xf7
-
# ATT: vcvttpd2udqs %ymm23, %xmm22 {%k7}
# INTEL: vcvttpd2udqs xmm22 {k7}, ymm23
0x62,0xa5,0xfc,0x2f,0x6c,0xf7
-# ATT: vcvttpd2udqs {sae}, %ymm23, %xmm22 {%k7} {z}
-# INTEL: vcvttpd2udqs xmm22 {k7} {z}, ymm23, {sae}
-0x62,0xa5,0xf8,0x9f,0x6c,0xf7
-
# ATT: vcvttpd2udqs %zmm23, %ymm22
# INTEL: vcvttpd2udqs ymm22, zmm23
0x62,0xa5,0xfc,0x48,0x6c,0xf7
@@ -349,18 +325,10 @@
# INTEL: vcvttpd2uqqs ymm22, ymm23
0x62,0xa5,0xfd,0x28,0x6c,0xf7
-# ATT: vcvttpd2uqqs {sae}, %ymm23, %ymm22
-# INTEL: vcvttpd2uqqs ymm22, ymm23, {sae}
-0x62,0xa5,0xf9,0x18,0x6c,0xf7
-
# ATT: vcvttpd2uqqs %ymm23, %ymm22 {%k7}
# INTEL: vcvttpd2uqqs ymm22 {k7}, ymm23
0x62,0xa5,0xfd,0x2f,0x6c,0xf7
-# ATT: vcvttpd2uqqs {sae}, %ymm23, %ymm22 {%k7} {z}
-# INTEL: vcvttpd2uqqs ymm22 {k7} {z}, ymm23, {sae}
-0x62,0xa5,0xf9,0x9f,0x6c,0xf7
-
# ATT: vcvttpd2uqqs %zmm23, %zmm22
# INTEL: vcvttpd2uqqs zmm22, zmm23
0x62,0xa5,0xfd,0x48,0x6c,0xf7
@@ -465,18 +433,10 @@
# INTEL: vcvttps2dqs ymm22, ymm23
0x62,0xa5,0x7c,0x28,0x6d,0xf7
-# ATT: vcvttps2dqs {sae}, %ymm23, %ymm22
-# INTEL: vcvttps2dqs ymm22, ymm23, {sae}
-0x62,0xa5,0x78,0x18,0x6d,0xf7
-
# ATT: vcvttps2dqs %ymm23, %ymm22 {%k7}
# INTEL: vcvttps2dqs ymm22 {k7}, ymm23
0x62,0xa5,0x7c,0x2f,0x6d,0xf7
-# ATT: vcvttps2dqs {sae}, %ymm23, %ymm22 {%k7} {z}
-# INTEL: vcvttps2dqs ymm22 {k7} {z}, ymm23, {sae}
-0x62,0xa5,0x78,0x9f,0x6d,0xf7
-
# ATT: vcvttps2dqs %zmm23, %zmm22
# INTEL: vcvttps2dqs zmm22, zmm23
0x62,0xa5,0x7c,0x48,0x6d,0xf7
@@ -697,18 +657,10 @@
# INTEL: vcvttps2udqs ymm22, ymm23
0x62,0xa5,0x7c,0x28,0x6c,0xf7
-# ATT: vcvttps2udqs {sae}, %ymm23, %ymm22
-# INTEL: vcvttps2udqs ymm22, ymm23, {sae}
-0x62,0xa5,0x78,0x18,0x6c,0xf7
-
# ATT: vcvttps2udqs %ymm23, %ymm22 {%k7}
# INTEL: vcvttps2udqs ymm22 {k7}, ymm23
0x62,0xa5,0x7c,0x2f,0x6c,0xf7
-# ATT: vcvttps2udqs {sae}, %ymm23, %ymm22 {%k7} {z}
-# INTEL: vcvttps2udqs ymm22 {k7} {z}, ymm23, {sae}
-0x62,0xa5,0x78,0x9f,0x6c,0xf7
-
# ATT: vcvttps2udqs %zmm23, %zmm22
# INTEL: vcvttps2udqs zmm22, zmm23
0x62,0xa5,0x7c,0x48,0x6c,0xf7
diff --git a/llvm/test/MC/X86/avx10_2satcvtds-32-att.s b/llvm/test/MC/X86/avx10_2satcvtds-32-att.s
index ec59839150b5f..f33e04b2db930 100644
--- a/llvm/test/MC/X86/avx10_2satcvtds-32-att.s
+++ b/llvm/test/MC/X86/avx10_2satcvtds-32-att.s
@@ -144,18 +144,10 @@
// CHECK: encoding: [0x62,0xf5,0xfc,0x28,0x6d,0xd3]
vcvttpd2dqs %ymm3, %xmm2
-// CHECK: vcvttpd2dqs {sae}, %ymm3, %xmm2
-// CHECK: encoding: [0x62,0xf5,0xf8,0x18,0x6d,0xd3]
- vcvttpd2dqs {sae}, %ymm3, %xmm2
-
// CHECK: vcvttpd2dqs %ymm3, %xmm2 {%k7}
// CHECK: encoding: [0x62,0xf5,0xfc,0x2f,0x6d,0xd3]
vcvttpd2dqs %ymm3, %xmm2 {%k7}
-// CHECK: vcvttpd2dqs {sae}, %ymm3, %xmm2 {%k7} {z}
-// CHECK: encoding: [0x62,0xf5,0xf8,0x9f,0x6d,0xd3]
- vcvttpd2dqs {sae}, %ymm3, %xmm2 {%k7} {z}
-
// CHECK: vcvttpd2dqs %zmm3, %ymm2
// CHECK: encoding: [0x62,0xf5,0xfc,0x48,0x6d,0xd3]
vcvttpd2dqs %zmm3, %ymm2
@@ -252,18 +244,10 @@
// CHECK: encoding: [0x62,0xf5,0xfd,0x28,0x6d,0xd3]
vcvttpd2qqs %ymm3, %ymm2
-// CHECK: vcvttpd2qqs {sae}, %ymm3, %ymm2
-// CHECK: encoding: [0x62,0xf5,0xf9,0x18,0x6d,0xd3]
- vcvttpd2qqs {sae}, %ymm3, %ymm2
-
// CHECK: vcvttpd2qqs %ymm3, %ymm2 {%k7}
// CHECK: encoding: [0x62,0xf5,0xfd,0x2f,0x6d,0xd3]
vcvttpd2qqs %ymm3, %ymm2 {%k7}
-// CHECK: vcvttpd2qqs {sae}, %ymm3, %ymm2 {%k7} {z}
-// CHECK: encoding: [0x62,0xf5,0xf9,0x9f,0x6d,0xd3]
- vcvttpd2qqs {sae}, %ymm3, %ymm2 {%k7} {z}
-
// CHECK: vcvttpd2qqs %zmm3, %zmm2
// CHECK: encoding: [0x62,0xf5,0xfd,0x48,0x6d,0xd3]
vcvttpd2qqs %zmm3, %zmm2
@@ -368,18 +352,10 @@
// CHECK: encoding: [0x62,0xf5,0xfc,0x28,0x6c,0xd3]
vcvttpd2udqs %ymm3, %xmm2
-// CHECK: vcvttpd2udqs {sae}, %ymm3, %xmm2
-// CHECK: encoding: [0x62,0xf5,0xf8,0x18,0x6c,0xd3]
- vcvttpd2udqs {sae}, %ymm3, %xmm2
-
// CHECK: vcvttpd2udqs %ymm3, %xmm2 {%k7}
// CHECK: encoding: [0x62,0xf5,0xfc,0x2f,0x6c,0xd3]
vcvttpd2udqs %ymm3, %xmm2 {%k7}
-// CHECK: vcvttpd2udqs {sae}, %ymm3, %xmm2 {%k7} {z}
-// CHECK: encoding: [0x62,0xf5,0xf8,0x9f,0x6c,0xd3]
- vcvttpd2udqs {sae}, %ymm3, %xmm2 {%k7} {z}
-
// CHECK: vcvttpd2udqs %zmm3, %ymm2
// CHECK: encoding: [0x62,0xf5,0xfc,0x48,0x6c,0xd3]
vcvttpd2udqs %zmm3, %ymm2
@@ -476,18 +452,10 @@
// CHECK: encoding: [0x62,0xf5,0xfd,0x28,0x6c,0xd3]
vcvttpd2uqqs %ymm3, %ymm2
-// CHECK: vcvttpd2uqqs {sae}, %ymm3, %ymm2
-// CHECK: encoding: [0x62,0xf5,0xf9,0x18,0x6c,0xd3]
- vcvttpd2uqqs {sae}, %ymm3, %ymm2
-
// CHECK: vcvttpd2uqqs %ymm3, %ymm2 {%k7}
// CHECK: encoding: [0x62,0xf5,0xfd,0x2f,0x6c,0xd3]
vcvttpd2uqqs %ymm3, %ymm2 {%k7}
-// CHECK: vcvttpd2uqqs {sae}, %ymm3, %ymm2 {%k7} {z}
-// CHECK: encoding: [0x62,0xf5,0xf9,0x9f,0x6c,0xd3]
- vcvttpd2uqqs {sae}, %ymm3, %ymm2 {%k7} {z}
-
// CHECK: vcvttpd2uqqs %zmm3, %zmm2
// CHECK: encoding: [0x62,0xf5,0xfd,0x48,0x6c,0xd3]
vcvttpd2uqqs %zmm3, %zmm2
@@ -592,18 +560,10 @@
// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x6d,0xd3]
vcvttps2dqs %ymm3, %ymm2
-// CHECK: vcvttps2dqs {sae}, %ymm3, %ymm2
-// CHECK: encoding: [0x62,0xf5,0x78,0x18,0x6d,0xd3]
- vcvttps2dqs {sae}, %ymm3, %ymm2
-
// CHECK: vcvttps2dqs %ymm3, %ymm2 {%k7}
// CHECK: encoding: [0x62,0xf5,0x7c,0x2f,0x6d,0xd3]
vcvttps2dqs %ymm3, %ymm2 {%k7}
-// CHECK: vcvttps2dqs {sae}, %ymm3, %ymm2 {%k7} {z}
-// CHECK: encoding: [0x62,0xf5,0x78,0x9f,0x6d,0xd3]
- vcvttps2dqs {sae}, %ymm3, %ymm2 {%k7} {z}
-
// CHECK: vcvttps2dqs %zmm3, %zmm2
// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x6d,0xd3]
vcvttps2dqs %zmm3, %zmm2
@@ -824,18 +784,10 @@
// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x6c,0xd3]
vcvttps2udqs %ymm3, %ymm2
-// CHECK: vcvttps2udqs {sae}, %ymm3, %ymm2
-// CHECK: encoding: [0x62,0xf5,0x78,0x18,0x6c,0xd3]
- vcvttps2udqs {sae}, %ymm3, %ymm2
-
// CHECK: vcvttps2udqs %ymm3, %ymm2 {%k7}
// CHECK: encoding: [0x62,0xf5,0x7c,0x2f,0x6c,0xd3]
vcvttps2udqs %ymm3, %ymm2 {%k7}
-// CHECK: vcvttps2udqs {sae}, %ymm3, %ymm2 {%k7} {z}
-// CHECK: encoding: [0x62,0xf5,0x78,0x9f,0x6c,0xd3]
- vcvttps2udqs {sae}, %ymm3, %ymm2 {%k7} {z}
-
// CHECK: vcvttps2udqs %zmm3, %zmm2
// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x6c,0xd3]
vcvttps2udqs %zmm3, %zmm2
diff --git a/llvm/test/MC/X86/avx10_2satcvtds-32-intel.s b/llvm/test/MC/X86/avx10_2satcvtds-32-intel.s
index 37a090de2f2ce..642df01fe8cdf 100644
--- a/llvm/test/MC/X86/avx10_2satcvtds-32-intel.s
+++ b/llvm/test/MC/X86/avx10_2satcvtds-32-intel.s
@@ -144,18 +144,10 @@
// CHECK: encoding: [0x62,0xf5,0xfc,0x28,0x6d,0xd3]
vcvttpd2dqs xmm2, ymm3
-// CHECK: vcvttpd2dqs xmm2, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0xf8,0x18,0x6d,0xd3]
- vcvttpd2dqs xmm2, ymm3, {sae}
-
// CHECK: vcvttpd2dqs xmm2 {k7}, ymm3
// CHECK: encoding: [0x62,0xf5,0xfc,0x2f,0x6d,0xd3]
vcvttpd2dqs xmm2 {k7}, ymm3
-// CHECK: vcvttpd2dqs xmm2 {k7} {z}, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0xf8,0x9f,0x6d,0xd3]
- vcvttpd2dqs xmm2 {k7} {z}, ymm3, {sae}
-
// CHECK: vcvttpd2dqs ymm2, zmm3
// CHECK: encoding: [0x62,0xf5,0xfc,0x48,0x6d,0xd3]
vcvttpd2dqs ymm2, zmm3
@@ -252,18 +244,10 @@
// CHECK: encoding: [0x62,0xf5,0xfd,0x28,0x6d,0xd3]
vcvttpd2qqs ymm2, ymm3
-// CHECK: vcvttpd2qqs ymm2, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0xf9,0x18,0x6d,0xd3]
- vcvttpd2qqs ymm2, ymm3, {sae}
-
// CHECK: vcvttpd2qqs ymm2 {k7}, ymm3
// CHECK: encoding: [0x62,0xf5,0xfd,0x2f,0x6d,0xd3]
vcvttpd2qqs ymm2 {k7}, ymm3
-// CHECK: vcvttpd2qqs ymm2 {k7} {z}, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0xf9,0x9f,0x6d,0xd3]
- vcvttpd2qqs ymm2 {k7} {z}, ymm3, {sae}
-
// CHECK: vcvttpd2qqs zmm2, zmm3
// CHECK: encoding: [0x62,0xf5,0xfd,0x48,0x6d,0xd3]
vcvttpd2qqs zmm2, zmm3
@@ -368,18 +352,10 @@
// CHECK: encoding: [0x62,0xf5,0xfc,0x28,0x6c,0xd3]
vcvttpd2udqs xmm2, ymm3
-// CHECK: vcvttpd2udqs xmm2, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0xf8,0x18,0x6c,0xd3]
- vcvttpd2udqs xmm2, ymm3, {sae}
-
// CHECK: vcvttpd2udqs xmm2 {k7}, ymm3
// CHECK: encoding: [0x62,0xf5,0xfc,0x2f,0x6c,0xd3]
vcvttpd2udqs xmm2 {k7}, ymm3
-// CHECK: vcvttpd2udqs xmm2 {k7} {z}, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0xf8,0x9f,0x6c,0xd3]
- vcvttpd2udqs xmm2 {k7} {z}, ymm3, {sae}
-
// CHECK: vcvttpd2udqs ymm2, zmm3
// CHECK: encoding: [0x62,0xf5,0xfc,0x48,0x6c,0xd3]
vcvttpd2udqs ymm2, zmm3
@@ -476,18 +452,10 @@
// CHECK: encoding: [0x62,0xf5,0xfd,0x28,0x6c,0xd3]
vcvttpd2uqqs ymm2, ymm3
-// CHECK: vcvttpd2uqqs ymm2, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0xf9,0x18,0x6c,0xd3]
- vcvttpd2uqqs ymm2, ymm3, {sae}
-
// CHECK: vcvttpd2uqqs ymm2 {k7}, ymm3
// CHECK: encoding: [0x62,0xf5,0xfd,0x2f,0x6c,0xd3]
vcvttpd2uqqs ymm2 {k7}, ymm3
-// CHECK: vcvttpd2uqqs ymm2 {k7} {z}, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0xf9,0x9f,0x6c,0xd3]
- vcvttpd2uqqs ymm2 {k7} {z}, ymm3, {sae}
-
// CHECK: vcvttpd2uqqs zmm2, zmm3
// CHECK: encoding: [0x62,0xf5,0xfd,0x48,0x6c,0xd3]
vcvttpd2uqqs zmm2, zmm3
@@ -592,18 +560,10 @@
// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x6d,0xd3]
vcvttps2dqs ymm2, ymm3
-// CHECK: vcvttps2dqs ymm2, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x78,0x18,0x6d,0xd3]
- vcvttps2dqs ymm2, ymm3, {sae}
-
// CHECK: vcvttps2dqs ymm2 {k7}, ymm3
// CHECK: encoding: [0x62,0xf5,0x7c,0x2f,0x6d,0xd3]
vcvttps2dqs ymm2 {k7}, ymm3
-// CHECK: vcvttps2dqs ymm2 {k7} {z}, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x78,0x9f,0x6d,0xd3]
- vcvttps2dqs ymm2 {k7} {z}, ymm3, {sae}
-
// CHECK: vcvttps2dqs zmm2, zmm3
// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x6d,0xd3]
vcvttps2dqs zmm2, zmm3
@@ -708,18 +668,10 @@
// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x6d,0xd3]
vcvttps2qqs ymm2, xmm3
-// CHECK: vcvttps2qqs ymm2, xmm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x79,0x18,0x6d,0xd3]
- vcvttps2qqs ymm2, xmm3, {sae}
-
// CHECK: vcvttps2qqs ymm2 {k7}, xmm3
// CHECK: encoding: [0x62,0xf5,0x7d,0x2f,0x6d,0xd3]
vcvttps2qqs ymm2 {k7}, xmm3
-// CHECK: vcvttps2qqs ymm2 {k7} {z}, xmm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x79,0x9f,0x6d,0xd3]
- vcvttps2qqs ymm2 {k7} {z}, xmm3, {sae}
-
// CHECK: vcvttps2qqs zmm2, ymm3
// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x6d,0xd3]
vcvttps2qqs zmm2, ymm3
@@ -824,18 +776,10 @@
// CHECK: encoding: [0x62,0xf5,0x7c,0x28,0x6c,0xd3]
vcvttps2udqs ymm2, ymm3
-// CHECK: vcvttps2udqs ymm2, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x78,0x18,0x6c,0xd3]
- vcvttps2udqs ymm2, ymm3, {sae}
-
// CHECK: vcvttps2udqs ymm2 {k7}, ymm3
// CHECK: encoding: [0x62,0xf5,0x7c,0x2f,0x6c,0xd3]
vcvttps2udqs ymm2 {k7}, ymm3
-// CHECK: vcvttps2udqs ymm2 {k7} {z}, ymm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x78,0x9f,0x6c,0xd3]
- vcvttps2udqs ymm2 {k7} {z}, ymm3, {sae}
-
// CHECK: vcvttps2udqs zmm2, zmm3
// CHECK: encoding: [0x62,0xf5,0x7c,0x48,0x6c,0xd3]
vcvttps2udqs zmm2, zmm3
@@ -940,18 +884,10 @@
// CHECK: encoding: [0x62,0xf5,0x7d,0x28,0x6c,0xd3]
vcvttps2uqqs ymm2, xmm3
-// CHECK: vcvttps2uqqs ymm2, xmm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x79,0x18,0x6c,0xd3]
- vcvttps2uqqs ymm2, xmm3, {sae}
-
// CHECK: vcvttps2uqqs ymm2 {k7}, xmm3
// CHECK: encoding: [0x62,0xf5,0x7d,0x2f,0x6c,0xd3]
vcvttps2uqqs ymm2 {k7}, xmm3
-// CHECK: vcvttps2uqqs ymm2 {k7} {z}, xmm3, {sae}
-// CHECK: encoding: [0x62,0xf5,0x79,0x9f,0x6c,0xd3]
- vcvttps2uqqs ymm2 {k7} {z}, xmm3, {sae}
-
// CHECK: vcvttps2uqqs zmm2, ymm3
// CHECK: encoding: [0x62,0xf5,0x7d,0x48,0x6c,0xd3]
vcvttps2uqqs zmm2, ymm3
diff --git a/llvm/test/MC/X86/avx10_2satcvtds-64-att.s b/llvm/test/MC/X86/avx10_2satcvtds-64-att.s
index c653bf52219a4..6218e726fa1a7 100644
--- a/llvm/test/MC/X86/avx10_2satcvtds-64-att.s
+++ b/llvm/test/MC/X86/avx10_2satcvtds-64-att.s
@@ -272,18 +272,10 @@
// CHECK: encoding: [0x62,0xa5,0xfc,0x28,0x6d,0xf7]
vcvttpd2dqs %ymm23, %xmm22
-// CHECK: vcvttpd2dqs {sae}, %ymm23, %xmm22
-// CHECK: encoding: [0x62,0xa5,0xf8,0x18,0x6d,0xf7]
- vcvttpd2dqs {sae}, %ymm23, %xmm22
-
// CHECK: vcvttpd2dqs %ymm23, %xmm22 {%k7}
// CHECK: encoding: [0x62,0xa5,0xfc,0x2f,0x6d,0xf7]
vcvttpd2dqs %ymm23, %xmm22 {%k7}
-// CHECK: vcvttpd2dqs {sae}, %ymm23, %xmm22 {%k7} {z}
-// CHECK: encoding: [0x62,0xa5,0xf8,0x9f,0x6d,0xf7]
- vcvttpd2dqs {sae}, %ymm23, %xmm22 {%k7} {z}
-
// CHECK: vcvttpd2dqs %zmm23, %ymm22
// CHECK: encoding: [0x62,0xa5,0xfc,0x48,0x6d,0xf7]
vcvttpd2dqs %zmm23, %ymm22
@@ -380,18 +372,10 @@
// CHECK: encoding: [0x62,0xa5,0xfd,0x28,0x6d,0xf7]
vcvttpd2qqs %ymm23, %ymm22
-// CHECK: vcvttpd2qqs {sae}, %ymm23, %ymm22
-// CHECK: encoding: [0x62,0xa5,0xf9,0x18,0x6d,0xf7]
- vcvttpd2qqs {sae}, %ymm23, %ymm22
-
// CHECK: vcvttpd2qqs %ymm23, %ymm22 {%k7}
// CHECK: encoding: [0x62,0xa5,0xfd,0x2f,0x6d,0xf7]
vcvttpd2qqs %ymm23, %ymm22 {%k7}
-// CHECK: vcvttpd2qqs {sae}, %ymm23, %ymm22 {%k7} {z}
-// CHECK: encoding: [0x62,0xa5,0xf9,0x9f,0x6d,0xf7]
- vcvttpd2qqs {sae}, %ymm23, %ymm22 {%k7} {z}
-
// CHECK: vcvttpd2qqs %zmm23, %zmm22
// CHECK: encoding: [0x62,0xa5,0xfd,0x48,0x6d,0xf7]
vcvttpd2qqs %zmm23, %zmm22
@@ -496,18 +480,10 @@
// CHECK: encoding: [0x62,0xa5,0xfc,0x28,0x6c,0xf7]
vcvttpd2udqs %ymm23, %xmm22
-// CHECK: vcvttpd2udqs {sae}, %ymm23, %xmm22
-// CHECK: encoding: [0x62,0xa5,0xf8,0x18,0x6c,0xf7]
- vcvttpd2udqs {sae}, %ymm23, %xmm22
-
// CHECK: vcvttpd2udqs %ymm23, %xmm22 {%k7}
// CHECK: encoding: [0x62,0xa5,0xfc,0x2f,0x6c,0xf7]
vcvttpd2udqs %ymm23, %xmm22 {%k7}
-// CHECK: vcvttpd2udqs {sae}, %ymm23, %xmm22 {%k7} {z}
-// CHECK: encoding: [0x62,0xa5,0xf8,0x9f,0x6c,0xf7]
- vcvttpd2udqs {sae}, %ymm23, %xmm22 {%k7} {z}
-
// CHECK: vcvttpd2udqs %zmm23, %ymm22
// CHECK: encoding: [0x62,0xa5,0xfc,0x48,0x6c,0xf7]
vcvttpd2udqs %zmm23, %ymm22
@@ -604,18 +580,10 @@
// CHECK: encoding: [0x62,0xa5,0xfd,0x28,0x6c,0xf7]
vcvttpd2uqqs %ymm23, %ymm22
-// CHECK: vcvttpd2uqqs {sae}, %ymm23, %ymm22
-// CHECK: encoding: [0x62,0xa5,0xf9,0x18,0x6c,0xf7]
- vcvttpd2uqqs {sae}, %ymm23, %ymm22
-
// CHECK: vcvttpd2uqqs %ymm23, %ymm22 {%k7}
// CHECK: encoding: [0x62,0xa5,0xfd,0x2f,0x6c,0xf7]
vcvttpd2uqqs %ymm23, %ymm22 {%k7}
-// CHECK: vcvttpd2uqqs {sae}, %ymm23, %ymm22 {%k7} {z}
-// CHECK: encoding: [0x62,0xa5,0xf9,0x9f,0x6c,0xf7]
- vcvttpd2uqqs {sae}, %ymm23, %ymm22 {%k7} {z}
-
// CHECK: vcvttpd2uqqs %zmm23, %zmm22
// CHECK: encoding: [0x62,0xa5,0xfd,0x48,0x6c,0xf7]
vcvttpd2uqqs %zmm23, %zmm22
@@ -720,18 +688,10 @@
// CHECK: encoding: [0x62,0xa5,0x7c,0x28,0x6d,0xf7]
vcvttps2dqs %ymm23, %ymm22
-// CHECK: vcvttps2dqs {sae}, %ymm23, %ymm22
-// CHECK: encoding: [0x62,0xa5,0x78,0x18,0x6d,0xf7]
- vcvttps2dqs {sae}, %ymm23, %ymm22
-
// CHECK: vcvttps2dqs %ymm23, %ymm22 {%k7}
// CHECK: encoding: [0x62,0xa5,0x7c,0x2f,0x6d,0xf7]
vcvttps2dqs %ymm23, %ymm22 {%k7}
-// CHECK: vcvttps2dqs {sae}, %ymm23, %ymm22 {%k7} {z}
-// CHECK: encoding: [0x62,0xa5,0x78,0x9f,0x6d,0xf7]
- vcvttps2dqs {sae}, %ymm23, %ymm22 {%k7} {z}
-
// CHECK: vcvttps2dqs %zmm23, %zmm22
// CHECK: encoding: [0x62,0xa5,0x7c,0x48,0x6d,0xf7]
vcvttps2dqs %zmm23, %zmm22
@@ -952,18 +912,10 @@
// CHECK: encoding: [0x62,0xa5,0x7c,0x28,0x6c,0xf7]
vcvttps2udqs %ymm23, %ymm22
-// CHECK: vcvttps2udqs {sae}, %ymm23, %ymm22
-// CHECK: encoding: [0x62,0xa5,0x78,0x18,0x6c,0xf7]
- vcvttps2udqs {sae}, %ymm23, %ymm22
-
// CHECK: vcvttps2udqs %ymm23, %ymm22 {%k7}
// CHECK: encoding: [0x62,0xa5,0x7c,0x2f,0x6c,0xf7]
vcvttps2udqs %ymm23, %ymm22 {%k7}
-// CHECK: vcvttps2udqs {sae}, %ymm23, %ymm22 {%k7} {z}
-// CHECK: encoding: [0x62,0xa5,0x78,0x9f,0x6c,0xf7]
- vcvttps2udqs {sae}, %ymm23, %ymm22 {%k7} {z}
-
// CHECK: vcvttps2udqs %zmm23, %zmm22
// CHECK: encoding: [0x62,0xa5,0x7c,0x48,0x6c,0xf7]
vcvttps2udqs %zmm23, %zmm22
diff --git a/llvm/test/MC/X86/avx10_2satcvtds-64-intel.s b/llvm/test/MC/X86/avx10_2satcvtds-64-intel.s
index 9e9af84c054ef..3269b2ca49a4f 100644
--- a/llvm/test/MC/X86/avx10_2satcvtds-64-intel.s
+++ b/llvm/test/MC/X86/avx10_2satcvtds-64-intel.s
@@ -272,18 +272,10 @@
// CHECK: encoding: [0x62,0xa5,0xfc,0x28,0x6d,0xf7]
vcvttpd2dqs xmm22, ymm23
-// CHECK: vcvttpd2dqs xmm22, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0xf8,0x18,0x6d,0xf7]
- vcvttpd2dqs xmm22, ymm23, {sae}
-
// CHECK: vcvttpd2dqs xmm22 {k7}, ymm23
// CHECK: encoding: [0x62,0xa5,0xfc,0x2f,0x6d,0xf7]
vcvttpd2dqs xmm22 {k7}, ymm23
-// CHECK: vcvttpd2dqs xmm22 {k7} {z}, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0xf8,0x9f,0x6d,0xf7]
- vcvttpd2dqs xmm22 {k7} {z}, ymm23, {sae}
-
// CHECK: vcvttpd2dqs ymm22, zmm23
// CHECK: encoding: [0x62,0xa5,0xfc,0x48,0x6d,0xf7]
vcvttpd2dqs ymm22, zmm23
@@ -380,18 +372,10 @@
// CHECK: encoding: [0x62,0xa5,0xfd,0x28,0x6d,0xf7]
vcvttpd2qqs ymm22, ymm23
-// CHECK: vcvttpd2qqs ymm22, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0xf9,0x18,0x6d,0xf7]
- vcvttpd2qqs ymm22, ymm23, {sae}
-
// CHECK: vcvttpd2qqs ymm22 {k7}, ymm23
// CHECK: encoding: [0x62,0xa5,0xfd,0x2f,0x6d,0xf7]
vcvttpd2qqs ymm22 {k7}, ymm23
-// CHECK: vcvttpd2qqs ymm22 {k7} {z}, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0xf9,0x9f,0x6d,0xf7]
- vcvttpd2qqs ymm22 {k7} {z}, ymm23, {sae}
-
// CHECK: vcvttpd2qqs zmm22, zmm23
// CHECK: encoding: [0x62,0xa5,0xfd,0x48,0x6d,0xf7]
vcvttpd2qqs zmm22, zmm23
@@ -496,18 +480,10 @@
// CHECK: encoding: [0x62,0xa5,0xfc,0x28,0x6c,0xf7]
vcvttpd2udqs xmm22, ymm23
-// CHECK: vcvttpd2udqs xmm22, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0xf8,0x18,0x6c,0xf7]
- vcvttpd2udqs xmm22, ymm23, {sae}
-
// CHECK: vcvttpd2udqs xmm22 {k7}, ymm23
// CHECK: encoding: [0x62,0xa5,0xfc,0x2f,0x6c,0xf7]
vcvttpd2udqs xmm22 {k7}, ymm23
-// CHECK: vcvttpd2udqs xmm22 {k7} {z}, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0xf8,0x9f,0x6c,0xf7]
- vcvttpd2udqs xmm22 {k7} {z}, ymm23, {sae}
-
// CHECK: vcvttpd2udqs ymm22, zmm23
// CHECK: encoding: [0x62,0xa5,0xfc,0x48,0x6c,0xf7]
vcvttpd2udqs ymm22, zmm23
@@ -604,18 +580,10 @@
// CHECK: encoding: [0x62,0xa5,0xfd,0x28,0x6c,0xf7]
vcvttpd2uqqs ymm22, ymm23
-// CHECK: vcvttpd2uqqs ymm22, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0xf9,0x18,0x6c,0xf7]
- vcvttpd2uqqs ymm22, ymm23, {sae}
-
// CHECK: vcvttpd2uqqs ymm22 {k7}, ymm23
// CHECK: encoding: [0x62,0xa5,0xfd,0x2f,0x6c,0xf7]
vcvttpd2uqqs ymm22 {k7}, ymm23
-// CHECK: vcvttpd2uqqs ymm22 {k7} {z}, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0xf9,0x9f,0x6c,0xf7]
- vcvttpd2uqqs ymm22 {k7} {z}, ymm23, {sae}
-
// CHECK: vcvttpd2uqqs zmm22, zmm23
// CHECK: encoding: [0x62,0xa5,0xfd,0x48,0x6c,0xf7]
vcvttpd2uqqs zmm22, zmm23
@@ -720,18 +688,10 @@
// CHECK: encoding: [0x62,0xa5,0x7c,0x28,0x6d,0xf7]
vcvttps2dqs ymm22, ymm23
-// CHECK: vcvttps2dqs ymm22, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x78,0x18,0x6d,0xf7]
- vcvttps2dqs ymm22, ymm23, {sae}
-
// CHECK: vcvttps2dqs ymm22 {k7}, ymm23
// CHECK: encoding: [0x62,0xa5,0x7c,0x2f,0x6d,0xf7]
vcvttps2dqs ymm22 {k7}, ymm23
-// CHECK: vcvttps2dqs ymm22 {k7} {z}, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x78,0x9f,0x6d,0xf7]
- vcvttps2dqs ymm22 {k7} {z}, ymm23, {sae}
-
// CHECK: vcvttps2dqs zmm22, zmm23
// CHECK: encoding: [0x62,0xa5,0x7c,0x48,0x6d,0xf7]
vcvttps2dqs zmm22, zmm23
@@ -836,18 +796,10 @@
// CHECK: encoding: [0x62,0xa5,0x7d,0x28,0x6d,0xf7]
vcvttps2qqs ymm22, xmm23
-// CHECK: vcvttps2qqs ymm22, xmm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x79,0x18,0x6d,0xf7]
- vcvttps2qqs ymm22, xmm23, {sae}
-
// CHECK: vcvttps2qqs ymm22 {k7}, xmm23
// CHECK: encoding: [0x62,0xa5,0x7d,0x2f,0x6d,0xf7]
vcvttps2qqs ymm22 {k7}, xmm23
-// CHECK: vcvttps2qqs ymm22 {k7} {z}, xmm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x79,0x9f,0x6d,0xf7]
- vcvttps2qqs ymm22 {k7} {z}, xmm23, {sae}
-
// CHECK: vcvttps2qqs zmm22, ymm23
// CHECK: encoding: [0x62,0xa5,0x7d,0x48,0x6d,0xf7]
vcvttps2qqs zmm22, ymm23
@@ -952,18 +904,10 @@
// CHECK: encoding: [0x62,0xa5,0x7c,0x28,0x6c,0xf7]
vcvttps2udqs ymm22, ymm23
-// CHECK: vcvttps2udqs ymm22, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x78,0x18,0x6c,0xf7]
- vcvttps2udqs ymm22, ymm23, {sae}
-
// CHECK: vcvttps2udqs ymm22 {k7}, ymm23
// CHECK: encoding: [0x62,0xa5,0x7c,0x2f,0x6c,0xf7]
vcvttps2udqs ymm22 {k7}, ymm23
-// CHECK: vcvttps2udqs ymm22 {k7} {z}, ymm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x78,0x9f,0x6c,0xf7]
- vcvttps2udqs ymm22 {k7} {z}, ymm23, {sae}
-
// CHECK: vcvttps2udqs zmm22, zmm23
// CHECK: encoding: [0x62,0xa5,0x7c,0x48,0x6c,0xf7]
vcvttps2udqs zmm22, zmm23
@@ -1068,18 +1012,10 @@
// CHECK: encoding: [0x62,0xa5,0x7d,0x28,0x6c,0xf7]
vcvttps2uqqs ymm22, xmm23
-// CHECK: vcvttps2uqqs ymm22, xmm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x79,0x18,0x6c,0xf7]
- vcvttps2uqqs ymm22, xmm23, {sae}
-
// CHECK: vcvttps2uqqs ymm22 {k7}, xmm23
// CHECK: encoding: [0x62,0xa5,0x7d,0x2f,0x6c,0xf7]
vcvttps2uqqs ymm22 {k7}, xmm23
-// CHECK: vcvttps2uqqs ymm22 {k7} {z}, xmm23, {sae}
-// CHECK: encoding: [0x62,0xa5,0x79,0x9f,0x6c,0xf7]
- vcvttps2uqqs ymm22 {k7} {z}, xmm23, {sae}
-
// CHECK: vcvttps2uqqs zmm22, ymm23
// CHECK: encoding: [0x62,0xa5,0x7d,0x48,0x6c,0xf7]
vcvttps2uqqs zmm22, ymm23
>From 1a2f8b75d63c698063526a2c22427e22b6c42eff Mon Sep 17 00:00:00 2001
From: "Wang, Phoebe" <phoebe.wang at intel.com>
Date: Sat, 22 Mar 2025 00:58:25 +0800
Subject: [PATCH 2/2] clang-format
---
clang/lib/Headers/avx10_2satcvtdsintrin.h | 32 +++++++++++------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/clang/lib/Headers/avx10_2satcvtdsintrin.h b/clang/lib/Headers/avx10_2satcvtdsintrin.h
index 6509a4ebf9c77..cc840368c308f 100644
--- a/clang/lib/Headers/avx10_2satcvtdsintrin.h
+++ b/clang/lib/Headers/avx10_2satcvtdsintrin.h
@@ -98,8 +98,8 @@ _mm256_cvtts_pd_epi32(__m256d __A) {
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_pd_epi32(__m128i __W, __mmask8 __U, __m256d __A) {
- return ((__m128i)__builtin_ia32_vcvttpd2dqs256_mask(
- (__v4df)__A, (__v4si)__W, __U));
+ return ((__m128i)__builtin_ia32_vcvttpd2dqs256_mask((__v4df)__A, (__v4si)__W,
+ __U));
}
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -136,8 +136,8 @@ _mm256_cvtts_pd_epu32(__m256d __A) {
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_pd_epu32(__m128i __W, __mmask8 __U, __m256d __A) {
- return ((__m128i)__builtin_ia32_vcvttpd2udqs256_mask(
- (__v4df)__A, (__v4si)__W, __U));
+ return ((__m128i)__builtin_ia32_vcvttpd2udqs256_mask((__v4df)__A, (__v4si)__W,
+ __U));
}
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -174,8 +174,8 @@ _mm256_cvtts_pd_epi64(__m256d __A) {
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_pd_epi64(__m256i __W, __mmask8 __U, __m256d __A) {
- return ((__m256i)__builtin_ia32_vcvttpd2qqs256_mask(
- (__v4df)__A, (__v4di)__W, __U));
+ return ((__m256i)__builtin_ia32_vcvttpd2qqs256_mask((__v4df)__A, (__v4di)__W,
+ __U));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -213,8 +213,8 @@ _mm256_cvtts_pd_epu64(__m256d __A) {
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_pd_epu64(__m256i __W, __mmask8 __U, __m256d __A) {
- return ((__m256i)__builtin_ia32_vcvttpd2uqqs256_mask(
- (__v4df)__A, (__v4di)__W, __U));
+ return ((__m256i)__builtin_ia32_vcvttpd2uqqs256_mask((__v4df)__A, (__v4di)__W,
+ __U));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -250,8 +250,8 @@ _mm256_cvtts_ps_epi32(__m256 __A) {
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_ps_epi32(__m256i __W, __mmask8 __U, __m256 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2dqs256_mask(
- (__v8sf)__A, (__v8si)__W, __U));
+ return ((__m256i)__builtin_ia32_vcvttps2dqs256_mask((__v8sf)__A, (__v8si)__W,
+ __U));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -288,8 +288,8 @@ _mm256_cvtts_ps_epu32(__m256 __A) {
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_ps_epu32(__m256i __W, __mmask8 __U, __m256 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2udqs256_mask(
- (__v8sf)__A, (__v8si)__W, __U));
+ return ((__m256i)__builtin_ia32_vcvttps2udqs256_mask((__v8sf)__A, (__v8si)__W,
+ __U));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -324,8 +324,8 @@ _mm256_cvtts_ps_epi64(__m128 __A) {
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_ps_epi64(__m256i __W, __mmask8 __U, __m128 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2qqs256_mask(
- (__v4sf)__A, (__v4di)__W, __U));
+ return ((__m256i)__builtin_ia32_vcvttps2qqs256_mask((__v4sf)__A, (__v4di)__W,
+ __U));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -361,8 +361,8 @@ _mm256_cvtts_ps_epu64(__m128 __A) {
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtts_ps_epu64(__m256i __W, __mmask8 __U, __m128 __A) {
- return ((__m256i)__builtin_ia32_vcvttps2uqqs256_mask(
- (__v4sf)__A, (__v4di)__W, __U));
+ return ((__m256i)__builtin_ia32_vcvttps2uqqs256_mask((__v4sf)__A, (__v4di)__W,
+ __U));
}
static __inline__ __m256i __DEFAULT_FN_ATTRS256
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