[llvm] [AMDGPU] Support block load/store for CSR (PR #130013)

[Matt Arsenault via llvm-commits]

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@@ -566,6 +576,13 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction,
   // frame, so save it here and add it to the RegScavenger later.
   std::optional<int> ScavengeFI;
 
+  // Map each VGPR CSR to the mask needed to save and restore it using block
+  // load/store instructions. Only used if the subtarget feature for VGPR block
+  // load/store is enabled.
+  // This is only useful during prolog/epilog insertion, so it doesn't need to
+  // be serialized.
+  IndexedMap<uint32_t, VGPRBlock2IndexFunctor> MaskForVGPRBlockOps;
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arsenm wrote:

I don't follow why this needs to be here. If it doesn't need serialization, it is pass local state that should not be here.  This is only used on instructions directly inserted in PEI. Why isn't this directly represented with a set of implicit uses (or a regmask) inline on the instruction? This seems like an avoidable intermediate state 

https://github.com/llvm/llvm-project/pull/130013