[llvm] [llvm][LoongArch] Changing the default code model from `small` to `medium` for 64-bit (PR #132173)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 20 04:55:44 PDT 2025
https://github.com/heiher updated https://github.com/llvm/llvm-project/pull/132173
>From f083204072f315829a0aa6a9f740c4a0898c2fb1 Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui at loongson.cn>
Date: Thu, 20 Mar 2025 16:58:39 +0800
Subject: [PATCH 1/2] [llvm][LoongArch] Changing the default code model from
`small` to `medium` for 64-bit
---
.../LoongArch/LoongArchTargetMachine.cpp | 2 +-
llvm/test/CodeGen/LoongArch/addrspacecast.ll | 3 +-
llvm/test/CodeGen/LoongArch/alloca.ll | 9 +-
llvm/test/CodeGen/LoongArch/analyze-branch.ll | 12 +-
llvm/test/CodeGen/LoongArch/bnez-beqz.ll | 12 +-
.../CodeGen/LoongArch/calling-conv-common.ll | 27 ++-
.../CodeGen/LoongArch/calling-conv-lp64d.ll | 9 +-
.../CodeGen/LoongArch/calling-conv-lp64s.ll | 12 +-
.../LoongArch/can-not-realign-stack.ll | 6 +-
llvm/test/CodeGen/LoongArch/double-br-fcmp.ll | 84 +++++---
llvm/test/CodeGen/LoongArch/double-lround.ll | 3 +-
.../duplicate-returns-for-tailcall.ll | 12 +-
llvm/test/CodeGen/LoongArch/eh-dwarf-cfa.ll | 3 +-
.../LoongArch/exception-pointer-register.ll | 12 +-
llvm/test/CodeGen/LoongArch/expand-call.ll | 4 +-
llvm/test/CodeGen/LoongArch/float-br-fcmp.ll | 84 +++++---
llvm/test/CodeGen/LoongArch/float-lround.ll | 3 +-
llvm/test/CodeGen/LoongArch/fp-expand.ll | 36 ++--
llvm/test/CodeGen/LoongArch/fp-max-min.ll | 6 +-
.../LoongArch/fp-maximumnum-minimumnum.ll | 18 +-
llvm/test/CodeGen/LoongArch/fp-reciprocal.ll | 3 +-
llvm/test/CodeGen/LoongArch/fp-rounding.ll | 24 ++-
llvm/test/CodeGen/LoongArch/fp-trunc-store.ll | 3 +-
llvm/test/CodeGen/LoongArch/fp16-promote.ll | 72 ++++---
llvm/test/CodeGen/LoongArch/frame.ll | 3 +-
llvm/test/CodeGen/LoongArch/frint.ll | 3 +-
llvm/test/CodeGen/LoongArch/fsqrt.ll | 9 +-
llvm/test/CodeGen/LoongArch/ghc-cc.ll | 3 +-
.../LoongArch/intrinsic-csr-side-effects.ll | 51 +++--
.../LoongArch/intrinsic-iocsr-side-effects.ll | 12 +-
.../ir-instruction/atomic-cmpxchg-128.ll | 21 +-
.../LoongArch/ir-instruction/atomicrmw-fp.ll | 180 ++++++++++++------
.../CodeGen/LoongArch/ir-instruction/call.ll | 6 +-
.../LoongArch/ir-instruction/float-convert.ll | 9 +-
llvm/test/CodeGen/LoongArch/lasx/fpowi.ll | 36 ++--
llvm/test/CodeGen/LoongArch/libcall-extend.ll | 9 +-
llvm/test/CodeGen/LoongArch/lsx/fpowi.ll | 18 +-
.../LoongArch/machinelicm-address-pseudos.ll | 6 +-
llvm/test/CodeGen/LoongArch/memcmp.ll | 3 +-
.../LoongArch/naked-fn-with-frame-pointer.ll | 6 +-
llvm/test/CodeGen/LoongArch/nomerge.ll | 15 +-
.../CodeGen/LoongArch/numeric-reg-names.ll | 3 +-
llvm/test/CodeGen/LoongArch/sextw-removal.ll | 78 +++++---
llvm/test/CodeGen/LoongArch/shrinkwrap.ll | 12 +-
llvm/test/CodeGen/LoongArch/soft-fp-to-int.ll | 18 +-
.../CodeGen/LoongArch/spill-reload-cfr.ll | 3 +-
.../test/CodeGen/LoongArch/split-sp-adjust.ll | 6 +-
...realignment-with-variable-sized-objects.ll | 3 +-
.../CodeGen/LoongArch/stack-realignment.ll | 48 +++--
.../LoongArch/statepoint-call-lowering.ll | 4 +-
llvm/test/CodeGen/LoongArch/tail-calls.ll | 27 ++-
.../target-abi-from-triple-edge-cases.ll | 12 +-
llvm/test/CodeGen/LoongArch/tls-models.ll | 6 +-
.../LoongArch/unaligned-memcpy-inline.ll | 3 +-
llvm/test/CodeGen/LoongArch/vararg.ll | 24 ++-
llvm/test/CodeGen/LoongArch/vector-fp-imm.ll | 42 ++--
56 files changed, 758 insertions(+), 380 deletions(-)
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
index 62b08be5435cd..692392dc2bae0 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
@@ -70,7 +70,7 @@ static CodeModel::Model
getEffectiveLoongArchCodeModel(const Triple &TT,
std::optional<CodeModel::Model> CM) {
if (!CM)
- return CodeModel::Small;
+ return TT.isArch64Bit() ? CodeModel::Medium : CodeModel::Small;
switch (*CM) {
case CodeModel::Small:
diff --git a/llvm/test/CodeGen/LoongArch/addrspacecast.ll b/llvm/test/CodeGen/LoongArch/addrspacecast.ll
index 1ca41705f9741..b177e8fc17dd6 100644
--- a/llvm/test/CodeGen/LoongArch/addrspacecast.ll
+++ b/llvm/test/CodeGen/LoongArch/addrspacecast.ll
@@ -35,7 +35,8 @@ define void @cast1(ptr %ptr) {
; LA64-NEXT: .cfi_def_cfa_offset 16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: .cfi_offset 1, -8
-; LA64-NEXT: bl %plt(foo)
+; LA64-NEXT: pcaddu18i $ra, %call36(foo)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/alloca.ll b/llvm/test/CodeGen/LoongArch/alloca.ll
index d298beaaa766c..effd7daffe610 100644
--- a/llvm/test/CodeGen/LoongArch/alloca.ll
+++ b/llvm/test/CodeGen/LoongArch/alloca.ll
@@ -39,7 +39,8 @@ define void @simple_alloca(i32 %n) nounwind {
; LA64-NEXT: slli.d $a0, $a0, 4
; LA64-NEXT: sub.d $a0, $sp, $a0
; LA64-NEXT: move $sp, $a0
-; LA64-NEXT: bl %plt(notdead)
+; LA64-NEXT: pcaddu18i $ra, %call36(notdead)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: addi.d $sp, $fp, -16
; LA64-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
@@ -89,7 +90,8 @@ define void @scoped_alloca(i32 %n) nounwind {
; LA64-NEXT: slli.d $a0, $a0, 4
; LA64-NEXT: sub.d $a0, $sp, $a0
; LA64-NEXT: move $sp, $a0
-; LA64-NEXT: bl %plt(notdead)
+; LA64-NEXT: pcaddu18i $ra, %call36(notdead)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: move $sp, $s0
; LA64-NEXT: addi.d $sp, $fp, -32
; LA64-NEXT: ld.d $s0, $sp, 8 # 8-byte Folded Reload
@@ -171,7 +173,8 @@ define void @alloca_callframe(i32 %n) nounwind {
; LA64-NEXT: ori $a6, $zero, 7
; LA64-NEXT: ori $a7, $zero, 8
; LA64-NEXT: st.d $t0, $sp, 0
-; LA64-NEXT: bl %plt(func)
+; LA64-NEXT: pcaddu18i $ra, %call36(func)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: addi.d $sp, $sp, 32
; LA64-NEXT: addi.d $sp, $fp, -16
; LA64-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/LoongArch/analyze-branch.ll b/llvm/test/CodeGen/LoongArch/analyze-branch.ll
index d15229a8c9e18..7cbcfb2c0fff4 100644
--- a/llvm/test/CodeGen/LoongArch/analyze-branch.ll
+++ b/llvm/test/CodeGen/LoongArch/analyze-branch.ll
@@ -19,13 +19,15 @@ define void @test_bcc_fallthrough_taken(i64 %in) nounwind {
; CHECK-NEXT: ori $a1, $zero, 42
; CHECK-NEXT: bne $a0, $a1, .LBB0_3
; CHECK-NEXT: # %bb.1: # %true
-; CHECK-NEXT: bl %plt(test_true)
+; CHECK-NEXT: pcaddu18i $ra, %call36(test_true)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: .LBB0_2: # %true
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_3: # %false
-; CHECK-NEXT: bl %plt(test_false)
+; CHECK-NEXT: pcaddu18i $ra, %call36(test_false)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: b .LBB0_2
%tst = icmp eq i64 %in, 42
br i1 %tst, label %true, label %false, !prof !0
@@ -51,13 +53,15 @@ define void @test_bcc_fallthrough_nottaken(i64 %in) nounwind {
; CHECK-NEXT: ori $a1, $zero, 42
; CHECK-NEXT: beq $a0, $a1, .LBB1_3
; CHECK-NEXT: # %bb.1: # %false
-; CHECK-NEXT: bl %plt(test_false)
+; CHECK-NEXT: pcaddu18i $ra, %call36(test_false)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: .LBB1_2: # %true
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_3: # %true
-; CHECK-NEXT: bl %plt(test_true)
+; CHECK-NEXT: pcaddu18i $ra, %call36(test_true)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: b .LBB1_2
%tst = icmp eq i64 %in, 42
br i1 %tst, label %true, label %false, !prof !1
diff --git a/llvm/test/CodeGen/LoongArch/bnez-beqz.ll b/llvm/test/CodeGen/LoongArch/bnez-beqz.ll
index b2d7f3fe41733..93bbcbbf2bf66 100644
--- a/llvm/test/CodeGen/LoongArch/bnez-beqz.ll
+++ b/llvm/test/CodeGen/LoongArch/bnez-beqz.ll
@@ -19,7 +19,8 @@ define void @bnez_i32(i32 signext %0) nounwind {
; LA64-NEXT: # %bb.1: # %f
; LA64-NEXT: ret
; LA64-NEXT: .LBB0_2: # %t
-; LA64-NEXT: b %plt(bar)
+; LA64-NEXT: pcaddu18i $t8, %call36(bar)
+; LA64-NEXT: jr $t8
start:
%1 = icmp eq i32 %0, 0
br i1 %1, label %t, label %f
@@ -45,7 +46,8 @@ define void @beqz_i32(i32 signext %0) nounwind {
; LA64: # %bb.0: # %start
; LA64-NEXT: beqz $a0, .LBB1_2
; LA64-NEXT: # %bb.1: # %t
-; LA64-NEXT: b %plt(bar)
+; LA64-NEXT: pcaddu18i $t8, %call36(bar)
+; LA64-NEXT: jr $t8
; LA64-NEXT: .LBB1_2: # %f
; LA64-NEXT: ret
start:
@@ -76,7 +78,8 @@ define void @bnez_i64(i64 %0) nounwind {
; LA64-NEXT: # %bb.1: # %f
; LA64-NEXT: ret
; LA64-NEXT: .LBB2_2: # %t
-; LA64-NEXT: b %plt(bar)
+; LA64-NEXT: pcaddu18i $t8, %call36(bar)
+; LA64-NEXT: jr $t8
start:
%1 = icmp eq i64 %0, 0
br i1 %1, label %t, label %f
@@ -103,7 +106,8 @@ define void @beqz_i64(i64 %0) nounwind {
; LA64: # %bb.0: # %start
; LA64-NEXT: beqz $a0, .LBB3_2
; LA64-NEXT: # %bb.1: # %t
-; LA64-NEXT: b %plt(bar)
+; LA64-NEXT: pcaddu18i $t8, %call36(bar)
+; LA64-NEXT: jr $t8
; LA64-NEXT: .LBB3_2: # %f
; LA64-NEXT: ret
start:
diff --git a/llvm/test/CodeGen/LoongArch/calling-conv-common.ll b/llvm/test/CodeGen/LoongArch/calling-conv-common.ll
index 5c9575b2baab1..d07e2914c753a 100644
--- a/llvm/test/CodeGen/LoongArch/calling-conv-common.ll
+++ b/llvm/test/CodeGen/LoongArch/calling-conv-common.ll
@@ -24,7 +24,8 @@ define i64 @caller_i128_in_regs() nounwind {
; CHECK-NEXT: ori $a0, $zero, 1
; CHECK-NEXT: ori $a1, $zero, 2
; CHECK-NEXT: move $a2, $zero
-; CHECK-NEXT: bl %plt(callee_i128_in_regs)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_i128_in_regs)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
@@ -82,7 +83,8 @@ define i64 @caller_many_scalars() nounwind {
; CHECK-NEXT: ori $a7, $zero, 7
; CHECK-NEXT: st.d $zero, $sp, 0
; CHECK-NEXT: move $a5, $zero
-; CHECK-NEXT: bl %plt(callee_many_scalars)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_many_scalars)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 32
; CHECK-NEXT: ret
@@ -133,7 +135,8 @@ define i64 @caller_large_scalars() nounwind {
; CHECK-NEXT: addi.d $a0, $sp, 32
; CHECK-NEXT: addi.d $a1, $sp, 0
; CHECK-NEXT: st.d $a2, $sp, 32
-; CHECK-NEXT: bl %plt(callee_large_scalars)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_large_scalars)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 72 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 80
; CHECK-NEXT: ret
@@ -197,7 +200,8 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
; CHECK-NEXT: ori $a6, $zero, 7
; CHECK-NEXT: addi.d $a7, $sp, 48
; CHECK-NEXT: vst $vr0, $sp, 56
-; CHECK-NEXT: bl %plt(callee_large_scalars_exhausted_regs)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_large_scalars_exhausted_regs)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 88 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 96
; CHECK-NEXT: ret
@@ -244,7 +248,8 @@ define i64 @caller_large_struct() nounwind {
; CHECK-NEXT: st.d $a2, $sp, 24
; CHECK-NEXT: st.d $a3, $sp, 32
; CHECK-NEXT: addi.d $a0, $sp, 8
-; CHECK-NEXT: bl %plt(callee_large_struct)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_large_struct)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 72 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 80
; CHECK-NEXT: ret
@@ -277,7 +282,8 @@ define i64 @caller_small_scalar_ret() nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi.d $sp, $sp, -16
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT: bl %plt(callee_small_scalar_ret)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_small_scalar_ret)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: addi.w $a2, $zero, -2
; CHECK-NEXT: xor $a0, $a0, $a2
; CHECK-NEXT: orn $a0, $a0, $a1
@@ -309,7 +315,8 @@ define i64 @caller_small_struct_ret() nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi.d $sp, $sp, -16
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT: bl %plt(callee_small_struct_ret)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_small_struct_ret)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: add.d $a0, $a0, $a1
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
@@ -344,7 +351,8 @@ define void @caller_large_scalar_ret() nounwind {
; CHECK-NEXT: addi.d $sp, $sp, -48
; CHECK-NEXT: st.d $ra, $sp, 40 # 8-byte Folded Spill
; CHECK-NEXT: addi.d $a0, $sp, 0
-; CHECK-NEXT: bl %plt(callee_large_scalar_ret)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_large_scalar_ret)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 40 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 48
; CHECK-NEXT: ret
@@ -383,7 +391,8 @@ define i64 @caller_large_struct_ret() nounwind {
; CHECK-NEXT: addi.d $sp, $sp, -48
; CHECK-NEXT: st.d $ra, $sp, 40 # 8-byte Folded Spill
; CHECK-NEXT: addi.d $a0, $sp, 8
-; CHECK-NEXT: bl %plt(callee_large_struct_ret)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_large_struct_ret)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $a0, $sp, 8
; CHECK-NEXT: ld.d $a1, $sp, 32
; CHECK-NEXT: add.d $a0, $a0, $a1
diff --git a/llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll b/llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll
index 35186b660c1e6..733c53697b987 100644
--- a/llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll
+++ b/llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll
@@ -31,7 +31,8 @@ define i64 @caller_float_in_fpr() nounwind {
; CHECK-NEXT: movgr2fr.w $fa0, $zero
; CHECK-NEXT: movgr2fr.d $fa1, $zero
; CHECK-NEXT: ori $a0, $zero, 1
-; CHECK-NEXT: bl %plt(callee_float_in_fpr)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_float_in_fpr)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
@@ -74,7 +75,8 @@ define i64 @caller_double_in_gpr_exhausted_fprs() nounwind {
; CHECK-NEXT: vldi $vr5, -1000
; CHECK-NEXT: vldi $vr6, -996
; CHECK-NEXT: vldi $vr7, -992
-; CHECK-NEXT: bl %plt(callee_double_in_gpr_exhausted_fprs)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_double_in_gpr_exhausted_fprs)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
@@ -99,7 +101,8 @@ define i64 @caller_double_ret() nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi.d $sp, $sp, -16
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT: bl %plt(callee_double_ret)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_double_ret)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.d $a0, $fa0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
diff --git a/llvm/test/CodeGen/LoongArch/calling-conv-lp64s.ll b/llvm/test/CodeGen/LoongArch/calling-conv-lp64s.ll
index a10d30c372f16..1598c0fc50712 100644
--- a/llvm/test/CodeGen/LoongArch/calling-conv-lp64s.ll
+++ b/llvm/test/CodeGen/LoongArch/calling-conv-lp64s.ll
@@ -11,7 +11,8 @@ define i64 @callee_float_in_regs(i64 %a, float %b) nounwind {
; CHECK-NEXT: st.d $fp, $sp, 0 # 8-byte Folded Spill
; CHECK-NEXT: move $fp, $a0
; CHECK-NEXT: move $a0, $a1
-; CHECK-NEXT: bl %plt(__fixsfdi)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__fixsfdi)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: add.d $a0, $fp, $a0
; CHECK-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
@@ -29,7 +30,8 @@ define i64 @caller_float_in_regs() nounwind {
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; CHECK-NEXT: lu12i.w $a1, 262144
; CHECK-NEXT: ori $a0, $zero, 1
-; CHECK-NEXT: bl %plt(callee_float_in_regs)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_float_in_regs)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
@@ -64,7 +66,8 @@ define i64 @caller_float_on_stack() nounwind {
; CHECK-NEXT: move $a3, $zero
; CHECK-NEXT: move $a5, $zero
; CHECK-NEXT: move $a7, $zero
-; CHECK-NEXT: bl %plt(callee_float_on_stack)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_float_on_stack)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
@@ -85,7 +88,8 @@ define i64 @caller_tiny_scalar_ret() nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi.d $sp, $sp, -16
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT: bl %plt(callee_tiny_scalar_ret)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_tiny_scalar_ret)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: addi.w $a0, $a0, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
diff --git a/llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll b/llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll
index 6d5cf5a942931..52d8dd05aaa4c 100644
--- a/llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll
+++ b/llvm/test/CodeGen/LoongArch/can-not-realign-stack.ll
@@ -33,7 +33,8 @@ define dso_local noundef signext i32 @main() nounwind {
; CHECK-NEXT: xvst $xr2, $sp, 200
; CHECK-NEXT: xvst $xr3, $sp, 232
; CHECK-NEXT: addi.d $a0, $sp, 136
-; CHECK-NEXT: bl %plt(foo)
+; CHECK-NEXT: pcaddu18i $ra, %call36(foo)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: xvld $xr0, $sp, 96 # 32-byte Folded Reload
; CHECK-NEXT: xvst $xr0, $sp, 136
; CHECK-NEXT: xvld $xr0, $sp, 64 # 32-byte Folded Reload
@@ -43,7 +44,8 @@ define dso_local noundef signext i32 @main() nounwind {
; CHECK-NEXT: xvld $xr0, $sp, 0 # 32-byte Folded Reload
; CHECK-NEXT: xvst $xr0, $sp, 232
; CHECK-NEXT: addi.d $a0, $sp, 136
-; CHECK-NEXT: bl %plt(bar)
+; CHECK-NEXT: pcaddu18i $ra, %call36(bar)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: move $a0, $zero
; CHECK-NEXT: ld.d $ra, $sp, 264 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 272
diff --git a/llvm/test/CodeGen/LoongArch/double-br-fcmp.ll b/llvm/test/CodeGen/LoongArch/double-br-fcmp.ll
index 50cbb11be2ef6..6a5b856a42b2e 100644
--- a/llvm/test/CodeGen/LoongArch/double-br-fcmp.ll
+++ b/llvm/test/CodeGen/LoongArch/double-br-fcmp.ll
@@ -25,7 +25,8 @@ define void @br_fcmp_oeq_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: .LBB0_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp oeq double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -56,7 +57,8 @@ define void @br_fcmp_oeq_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: .LBB1_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp oeq double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -87,7 +89,8 @@ define void @br_fcmp_ogt_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: .LBB2_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ogt double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -118,7 +121,8 @@ define void @br_fcmp_ogt_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: .LBB3_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ogt double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -149,7 +153,8 @@ define void @br_fcmp_oge_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: .LBB4_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp oge double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -180,7 +185,8 @@ define void @br_fcmp_oge_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: .LBB5_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp oge double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -211,7 +217,8 @@ define void @br_fcmp_olt_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: .LBB6_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp olt double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -242,7 +249,8 @@ define void @br_fcmp_olt_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: .LBB7_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp olt double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -273,7 +281,8 @@ define void @br_fcmp_ole_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: .LBB8_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ole double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -304,7 +313,8 @@ define void @br_fcmp_ole_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: .LBB9_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ole double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -335,7 +345,8 @@ define void @br_fcmp_one_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: .LBB10_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp one double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -366,7 +377,8 @@ define void @br_fcmp_one_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: .LBB11_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp one double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -397,7 +409,8 @@ define void @br_fcmp_ord_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: .LBB12_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ord double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -428,7 +441,8 @@ define void @br_fcmp_ord_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: .LBB13_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ord double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -459,7 +473,8 @@ define void @br_fcmp_ueq_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: .LBB14_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ueq double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -490,7 +505,8 @@ define void @br_fcmp_ueq_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: .LBB15_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ueq double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -521,7 +537,8 @@ define void @br_fcmp_ugt_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: .LBB16_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ugt double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -552,7 +569,8 @@ define void @br_fcmp_ugt_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: .LBB17_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ugt double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -583,7 +601,8 @@ define void @br_fcmp_uge_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: .LBB18_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp uge double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -614,7 +633,8 @@ define void @br_fcmp_uge_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: .LBB19_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp uge double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -645,7 +665,8 @@ define void @br_fcmp_ult_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: .LBB20_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ult double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -676,7 +697,8 @@ define void @br_fcmp_ult_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: .LBB21_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ult double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -707,7 +729,8 @@ define void @br_fcmp_ule_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: .LBB22_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ule double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -738,7 +761,8 @@ define void @br_fcmp_ule_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: .LBB23_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ule double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -769,7 +793,8 @@ define void @br_fcmp_une_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: .LBB24_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp une double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -800,7 +825,8 @@ define void @br_fcmp_une_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: .LBB25_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp une double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -831,7 +857,8 @@ define void @br_fcmp_uno_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: .LBB26_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp uno double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -862,7 +889,8 @@ define void @br_fcmp_uno_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: .LBB27_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp uno double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
diff --git a/llvm/test/CodeGen/LoongArch/double-lround.ll b/llvm/test/CodeGen/LoongArch/double-lround.ll
index 1b7791d683973..a0ceffd22a697 100644
--- a/llvm/test/CodeGen/LoongArch/double-lround.ll
+++ b/llvm/test/CodeGen/LoongArch/double-lround.ll
@@ -9,7 +9,8 @@ define i32 @lround_i32_f64(double %a) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi.d $sp, $sp, -16
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT: bl %plt(lround)
+; CHECK-NEXT: pcaddu18i $ra, %call36(lround)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/duplicate-returns-for-tailcall.ll b/llvm/test/CodeGen/LoongArch/duplicate-returns-for-tailcall.ll
index ac9d885c7ce08..5a4aaa7ec194e 100644
--- a/llvm/test/CodeGen/LoongArch/duplicate-returns-for-tailcall.ll
+++ b/llvm/test/CodeGen/LoongArch/duplicate-returns-for-tailcall.ll
@@ -17,13 +17,17 @@ define i32 @duplicate_returns(i32 %a, i32 %b) nounwind {
; CHECK-NEXT: # %bb.2: # %if.else2
; CHECK-NEXT: bge $a1, $a0, .LBB0_6
; CHECK-NEXT: # %bb.3: # %if.then3
-; CHECK-NEXT: b %plt(test2)
+; CHECK-NEXT: pcaddu18i $t8, %call36(test2)
+; CHECK-NEXT: jr $t8
; CHECK-NEXT: .LBB0_4: # %if.then
-; CHECK-NEXT: b %plt(test)
+; CHECK-NEXT: pcaddu18i $t8, %call36(test)
+; CHECK-NEXT: jr $t8
; CHECK-NEXT: .LBB0_5: # %if.then2
-; CHECK-NEXT: b %plt(test1)
+; CHECK-NEXT: pcaddu18i $t8, %call36(test1)
+; CHECK-NEXT: jr $t8
; CHECK-NEXT: .LBB0_6: # %if.else3
-; CHECK-NEXT: b %plt(test3)
+; CHECK-NEXT: pcaddu18i $t8, %call36(test3)
+; CHECK-NEXT: jr $t8
entry:
%cmp = icmp eq i32 %a, 0
br i1 %cmp, label %if.then, label %if.else
diff --git a/llvm/test/CodeGen/LoongArch/eh-dwarf-cfa.ll b/llvm/test/CodeGen/LoongArch/eh-dwarf-cfa.ll
index f00cf9491c089..f23c5364b93e0 100644
--- a/llvm/test/CodeGen/LoongArch/eh-dwarf-cfa.ll
+++ b/llvm/test/CodeGen/LoongArch/eh-dwarf-cfa.ll
@@ -22,7 +22,8 @@ define void @dwarf() {
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: .cfi_offset 1, -8
; LA64-NEXT: addi.d $a0, $sp, 16
-; LA64-NEXT: bl %plt(foo)
+; LA64-NEXT: pcaddu18i $ra, %call36(foo)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/exception-pointer-register.ll b/llvm/test/CodeGen/LoongArch/exception-pointer-register.ll
index 530d97ff4bab9..91fa34aa3acfb 100644
--- a/llvm/test/CodeGen/LoongArch/exception-pointer-register.ll
+++ b/llvm/test/CodeGen/LoongArch/exception-pointer-register.ll
@@ -65,13 +65,15 @@ define void @caller(ptr %p) personality ptr @__gxx_personality_v0 {
; LA64-NEXT: # %bb.1: # %bb2
; LA64-NEXT: .Ltmp0:
; LA64-NEXT: move $a0, $fp
-; LA64-NEXT: bl %plt(bar)
+; LA64-NEXT: pcaddu18i $ra, %call36(bar)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: .Ltmp1:
; LA64-NEXT: b .LBB0_3
; LA64-NEXT: .LBB0_2: # %bb1
; LA64-NEXT: .Ltmp2:
; LA64-NEXT: move $a0, $fp
-; LA64-NEXT: bl %plt(foo)
+; LA64-NEXT: pcaddu18i $ra, %call36(foo)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: .Ltmp3:
; LA64-NEXT: .LBB0_3: # %end2
; LA64-NEXT: ld.d $s0, $sp, 8 # 8-byte Folded Reload
@@ -83,9 +85,11 @@ define void @caller(ptr %p) personality ptr @__gxx_personality_v0 {
; LA64-NEXT: .Ltmp4:
; LA64-NEXT: move $s0, $a0
; LA64-NEXT: move $a0, $fp
-; LA64-NEXT: bl callee
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: move $a0, $s0
-; LA64-NEXT: bl %plt(_Unwind_Resume)
+; LA64-NEXT: pcaddu18i $ra, %call36(_Unwind_Resume)
+; LA64-NEXT: jirl $ra, $ra, 0
entry:
%0 = icmp eq ptr %p, null
br i1 %0, label %bb1, label %bb2
diff --git a/llvm/test/CodeGen/LoongArch/expand-call.ll b/llvm/test/CodeGen/LoongArch/expand-call.ll
index d221200401bc5..495cf04c95b32 100644
--- a/llvm/test/CodeGen/LoongArch/expand-call.ll
+++ b/llvm/test/CodeGen/LoongArch/expand-call.ll
@@ -1,6 +1,6 @@
-; RUN: llc --mtriple=loongarch64 -mattr=+d --stop-before loongarch-prera-expand-pseudo \
+; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=small --stop-before loongarch-prera-expand-pseudo \
; RUN: --verify-machineinstrs < %s | FileCheck %s --check-prefix=NOEXPAND
-; RUN: llc --mtriple=loongarch64 --stop-after loongarch-prera-expand-pseudo \
+; RUN: llc --mtriple=loongarch64 -mattr=+d --code-model=small --stop-after loongarch-prera-expand-pseudo \
; RUN: --verify-machineinstrs < %s | FileCheck %s --check-prefix=EXPAND
declare void @callee()
diff --git a/llvm/test/CodeGen/LoongArch/float-br-fcmp.ll b/llvm/test/CodeGen/LoongArch/float-br-fcmp.ll
index a5edc9aa2c6e9..316cd7c37f217 100644
--- a/llvm/test/CodeGen/LoongArch/float-br-fcmp.ll
+++ b/llvm/test/CodeGen/LoongArch/float-br-fcmp.ll
@@ -25,7 +25,8 @@ define void @br_fcmp_oeq_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB0_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp oeq float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -56,7 +57,8 @@ define void @br_fcmp_oeq_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB1_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp oeq float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -87,7 +89,8 @@ define void @br_fcmp_ogt_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB2_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ogt float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -118,7 +121,8 @@ define void @br_fcmp_ogt_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB3_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ogt float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -149,7 +153,8 @@ define void @br_fcmp_oge_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB4_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp oge float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -180,7 +185,8 @@ define void @br_fcmp_oge_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB5_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp oge float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -211,7 +217,8 @@ define void @br_fcmp_olt_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB6_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp olt float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -242,7 +249,8 @@ define void @br_fcmp_olt_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB7_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp olt float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -273,7 +281,8 @@ define void @br_fcmp_ole_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB8_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ole float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -304,7 +313,8 @@ define void @br_fcmp_ole_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB9_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ole float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -335,7 +345,8 @@ define void @br_fcmp_one_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB10_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp one float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -366,7 +377,8 @@ define void @br_fcmp_one_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB11_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp one float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -397,7 +409,8 @@ define void @br_fcmp_ord_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB12_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ord float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -428,7 +441,8 @@ define void @br_fcmp_ord_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB13_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ord float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -459,7 +473,8 @@ define void @br_fcmp_ueq_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB14_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ueq float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -490,7 +505,8 @@ define void @br_fcmp_ueq_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB15_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ueq float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -521,7 +537,8 @@ define void @br_fcmp_ugt_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB16_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ugt float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -552,7 +569,8 @@ define void @br_fcmp_ugt_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB17_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ugt float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -583,7 +601,8 @@ define void @br_fcmp_uge_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB18_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp uge float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -614,7 +633,8 @@ define void @br_fcmp_uge_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB19_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp uge float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -645,7 +665,8 @@ define void @br_fcmp_ult_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB20_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ult float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -676,7 +697,8 @@ define void @br_fcmp_ult_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB21_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ult float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -707,7 +729,8 @@ define void @br_fcmp_ule_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB22_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ule float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -738,7 +761,8 @@ define void @br_fcmp_ule_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB23_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp ule float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -769,7 +793,8 @@ define void @br_fcmp_une_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB24_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp une float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -800,7 +825,8 @@ define void @br_fcmp_une_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB25_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp une float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -831,7 +857,8 @@ define void @br_fcmp_uno_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB26_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp uno float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -862,7 +889,8 @@ define void @br_fcmp_uno_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: .LBB27_2: # %if.then
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: pcaddu18i $ra, %call36(abort)
+; LA64-NEXT: jirl $ra, $ra, 0
%1 = fcmp uno float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
diff --git a/llvm/test/CodeGen/LoongArch/float-lround.ll b/llvm/test/CodeGen/LoongArch/float-lround.ll
index a129aa27a3e3e..720b50eba66bf 100644
--- a/llvm/test/CodeGen/LoongArch/float-lround.ll
+++ b/llvm/test/CodeGen/LoongArch/float-lround.ll
@@ -9,7 +9,8 @@ define i32 @lround_i32_f32(float %a) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: addi.d $sp, $sp, -16
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT: bl %plt(lroundf)
+; CHECK-NEXT: pcaddu18i $ra, %call36(lroundf)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/fp-expand.ll b/llvm/test/CodeGen/LoongArch/fp-expand.ll
index 7b5be82ef6549..0939094dae23a 100644
--- a/llvm/test/CodeGen/LoongArch/fp-expand.ll
+++ b/llvm/test/CodeGen/LoongArch/fp-expand.ll
@@ -18,7 +18,8 @@ define float @sin_f32(float %a) nounwind {
;
; LA64-LABEL: sin_f32:
; LA64: # %bb.0:
-; LA64-NEXT: b %plt(sinf)
+; LA64-NEXT: pcaddu18i $t8, %call36(sinf)
+; LA64-NEXT: jr $t8
%1 = call float @llvm.sin.f32(float %a)
ret float %1
}
@@ -30,7 +31,8 @@ define float @cos_f32(float %a) nounwind {
;
; LA64-LABEL: cos_f32:
; LA64: # %bb.0:
-; LA64-NEXT: b %plt(cosf)
+; LA64-NEXT: pcaddu18i $t8, %call36(cosf)
+; LA64-NEXT: jr $t8
%1 = call float @llvm.cos.f32(float %a)
ret float %1
}
@@ -61,10 +63,12 @@ define float @sincos_f32(float %a) nounwind {
; LA64-NEXT: fst.d $fs0, $sp, 16 # 8-byte Folded Spill
; LA64-NEXT: fst.d $fs1, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: fmov.s $fs0, $fa0
-; LA64-NEXT: bl %plt(sinf)
+; LA64-NEXT: pcaddu18i $ra, %call36(sinf)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fmov.s $fs1, $fa0
; LA64-NEXT: fmov.s $fa0, $fs0
-; LA64-NEXT: bl %plt(cosf)
+; LA64-NEXT: pcaddu18i $ra, %call36(cosf)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fadd.s $fa0, $fs1, $fa0
; LA64-NEXT: fld.d $fs1, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: fld.d $fs0, $sp, 16 # 8-byte Folded Reload
@@ -84,7 +88,8 @@ define float @pow_f32(float %a, float %b) nounwind {
;
; LA64-LABEL: pow_f32:
; LA64: # %bb.0:
-; LA64-NEXT: b %plt(powf)
+; LA64-NEXT: pcaddu18i $t8, %call36(powf)
+; LA64-NEXT: jr $t8
%1 = call float @llvm.pow.f32(float %a, float %b)
ret float %1
}
@@ -96,7 +101,8 @@ define float @frem_f32(float %a, float %b) nounwind {
;
; LA64-LABEL: frem_f32:
; LA64: # %bb.0:
-; LA64-NEXT: b %plt(fmodf)
+; LA64-NEXT: pcaddu18i $t8, %call36(fmodf)
+; LA64-NEXT: jr $t8
%1 = frem float %a, %b
ret float %1
}
@@ -108,7 +114,8 @@ define double @sin_f64(double %a) nounwind {
;
; LA64-LABEL: sin_f64:
; LA64: # %bb.0:
-; LA64-NEXT: b %plt(sin)
+; LA64-NEXT: pcaddu18i $t8, %call36(sin)
+; LA64-NEXT: jr $t8
%1 = call double @llvm.sin.f64(double %a)
ret double %1
}
@@ -120,7 +127,8 @@ define double @cos_f64(double %a) nounwind {
;
; LA64-LABEL: cos_f64:
; LA64: # %bb.0:
-; LA64-NEXT: b %plt(cos)
+; LA64-NEXT: pcaddu18i $t8, %call36(cos)
+; LA64-NEXT: jr $t8
%1 = call double @llvm.cos.f64(double %a)
ret double %1
}
@@ -151,10 +159,12 @@ define double @sincos_f64(double %a) nounwind {
; LA64-NEXT: fst.d $fs0, $sp, 16 # 8-byte Folded Spill
; LA64-NEXT: fst.d $fs1, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: fmov.d $fs0, $fa0
-; LA64-NEXT: bl %plt(sin)
+; LA64-NEXT: pcaddu18i $ra, %call36(sin)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fmov.d $fs1, $fa0
; LA64-NEXT: fmov.d $fa0, $fs0
-; LA64-NEXT: bl %plt(cos)
+; LA64-NEXT: pcaddu18i $ra, %call36(cos)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fadd.d $fa0, $fs1, $fa0
; LA64-NEXT: fld.d $fs1, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: fld.d $fs0, $sp, 16 # 8-byte Folded Reload
@@ -174,7 +184,8 @@ define double @pow_f64(double %a, double %b) nounwind {
;
; LA64-LABEL: pow_f64:
; LA64: # %bb.0:
-; LA64-NEXT: b %plt(pow)
+; LA64-NEXT: pcaddu18i $t8, %call36(pow)
+; LA64-NEXT: jr $t8
%1 = call double @llvm.pow.f64(double %a, double %b)
ret double %1
}
@@ -186,7 +197,8 @@ define double @frem_f64(double %a, double %b) nounwind {
;
; LA64-LABEL: frem_f64:
; LA64: # %bb.0:
-; LA64-NEXT: b %plt(fmod)
+; LA64-NEXT: pcaddu18i $t8, %call36(fmod)
+; LA64-NEXT: jr $t8
%1 = frem double %a, %b
ret double %1
}
diff --git a/llvm/test/CodeGen/LoongArch/fp-max-min.ll b/llvm/test/CodeGen/LoongArch/fp-max-min.ll
index b2ca475b16ab4..1adf4273b3158 100644
--- a/llvm/test/CodeGen/LoongArch/fp-max-min.ll
+++ b/llvm/test/CodeGen/LoongArch/fp-max-min.ll
@@ -66,7 +66,8 @@ define double @maxnum_double(double %x, double %y) {
; LA64F-NEXT: .cfi_def_cfa_offset 16
; LA64F-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64F-NEXT: .cfi_offset 1, -8
-; LA64F-NEXT: bl %plt(fmax)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fmax)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64F-NEXT: addi.d $sp, $sp, 16
; LA64F-NEXT: ret
@@ -138,7 +139,8 @@ define double @minnum_double(double %x, double %y) {
; LA64F-NEXT: .cfi_def_cfa_offset 16
; LA64F-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64F-NEXT: .cfi_offset 1, -8
-; LA64F-NEXT: bl %plt(fmin)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fmin)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64F-NEXT: addi.d $sp, $sp, 16
; LA64F-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/fp-maximumnum-minimumnum.ll b/llvm/test/CodeGen/LoongArch/fp-maximumnum-minimumnum.ll
index b4fdd954b856c..607e50cb5a6c6 100644
--- a/llvm/test/CodeGen/LoongArch/fp-maximumnum-minimumnum.ll
+++ b/llvm/test/CodeGen/LoongArch/fp-maximumnum-minimumnum.ll
@@ -127,7 +127,8 @@ define double @maximumnum_double(double %x, double %y) {
; LA64F-NEXT: .cfi_def_cfa_offset 16
; LA64F-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64F-NEXT: .cfi_offset 1, -8
-; LA64F-NEXT: bl %plt(fmaximum_num)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fmaximum_num)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64F-NEXT: addi.d $sp, $sp, 16
; LA64F-NEXT: ret
@@ -168,7 +169,8 @@ define double @maximumnum_double_nsz(double %x, double %y) {
; LA64F-NEXT: .cfi_def_cfa_offset 16
; LA64F-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64F-NEXT: .cfi_offset 1, -8
-; LA64F-NEXT: bl %plt(fmaximum_num)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fmaximum_num)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64F-NEXT: addi.d $sp, $sp, 16
; LA64F-NEXT: ret
@@ -207,7 +209,8 @@ define double @maximumnum_double_nnan(double %x, double %y) {
; LA64F-NEXT: .cfi_def_cfa_offset 16
; LA64F-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64F-NEXT: .cfi_offset 1, -8
-; LA64F-NEXT: bl %plt(fmaximum_num)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fmaximum_num)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64F-NEXT: addi.d $sp, $sp, 16
; LA64F-NEXT: ret
@@ -337,7 +340,8 @@ define double @minimumnum_double(double %x, double %y) {
; LA64F-NEXT: .cfi_def_cfa_offset 16
; LA64F-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64F-NEXT: .cfi_offset 1, -8
-; LA64F-NEXT: bl %plt(fminimum_num)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fminimum_num)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64F-NEXT: addi.d $sp, $sp, 16
; LA64F-NEXT: ret
@@ -378,7 +382,8 @@ define double @minimumnum_double_nsz(double %x, double %y) {
; LA64F-NEXT: .cfi_def_cfa_offset 16
; LA64F-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64F-NEXT: .cfi_offset 1, -8
-; LA64F-NEXT: bl %plt(fminimum_num)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fminimum_num)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64F-NEXT: addi.d $sp, $sp, 16
; LA64F-NEXT: ret
@@ -417,7 +422,8 @@ define double @minimumnum_double_nnan(double %x, double %y) {
; LA64F-NEXT: .cfi_def_cfa_offset 16
; LA64F-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64F-NEXT: .cfi_offset 1, -8
-; LA64F-NEXT: bl %plt(fminimum_num)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fminimum_num)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64F-NEXT: addi.d $sp, $sp, 16
; LA64F-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/fp-reciprocal.ll b/llvm/test/CodeGen/LoongArch/fp-reciprocal.ll
index b858099839cac..04caf2555fca6 100644
--- a/llvm/test/CodeGen/LoongArch/fp-reciprocal.ll
+++ b/llvm/test/CodeGen/LoongArch/fp-reciprocal.ll
@@ -54,7 +54,8 @@ define double @f64_reciprocal(double %a) nounwind {
; LA64F-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64F-NEXT: move $a1, $a0
; LA64F-NEXT: lu52i.d $a0, $zero, 1023
-; LA64F-NEXT: bl %plt(__divdf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__divdf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64F-NEXT: addi.d $sp, $sp, 16
; LA64F-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/fp-rounding.ll b/llvm/test/CodeGen/LoongArch/fp-rounding.ll
index 2f4d4eafafe0b..9c52cd9b02641 100644
--- a/llvm/test/CodeGen/LoongArch/fp-rounding.ll
+++ b/llvm/test/CodeGen/LoongArch/fp-rounding.ll
@@ -6,7 +6,8 @@
define float @ceil_f32(float %i) nounwind {
; NOLSX-LABEL: ceil_f32:
; NOLSX: # %bb.0: # %entry
-; NOLSX-NEXT: b %plt(ceilf)
+; NOLSX-NEXT: pcaddu18i $t8, %call36(ceilf)
+; NOLSX-NEXT: jr $t8
;
; LSX-LABEL: ceil_f32:
; LSX: # %bb.0: # %entry
@@ -24,7 +25,8 @@ entry:
define double @ceil_f64(double %i) nounwind {
; NOLSX-LABEL: ceil_f64:
; NOLSX: # %bb.0: # %entry
-; NOLSX-NEXT: b %plt(ceil)
+; NOLSX-NEXT: pcaddu18i $t8, %call36(ceil)
+; NOLSX-NEXT: jr $t8
;
; LSX-LABEL: ceil_f64:
; LSX: # %bb.0: # %entry
@@ -42,7 +44,8 @@ entry:
define float @floor_f32(float %i) nounwind {
; NOLSX-LABEL: floor_f32:
; NOLSX: # %bb.0: # %entry
-; NOLSX-NEXT: b %plt(floorf)
+; NOLSX-NEXT: pcaddu18i $t8, %call36(floorf)
+; NOLSX-NEXT: jr $t8
;
; LSX-LABEL: floor_f32:
; LSX: # %bb.0: # %entry
@@ -60,7 +63,8 @@ entry:
define double @floor_f64(double %i) nounwind {
; NOLSX-LABEL: floor_f64:
; NOLSX: # %bb.0: # %entry
-; NOLSX-NEXT: b %plt(floor)
+; NOLSX-NEXT: pcaddu18i $t8, %call36(floor)
+; NOLSX-NEXT: jr $t8
;
; LSX-LABEL: floor_f64:
; LSX: # %bb.0: # %entry
@@ -78,7 +82,8 @@ entry:
define float @trunc_f32(float %i) nounwind {
; NOLSX-LABEL: trunc_f32:
; NOLSX: # %bb.0: # %entry
-; NOLSX-NEXT: b %plt(truncf)
+; NOLSX-NEXT: pcaddu18i $t8, %call36(truncf)
+; NOLSX-NEXT: jr $t8
;
; LSX-LABEL: trunc_f32:
; LSX: # %bb.0: # %entry
@@ -96,7 +101,8 @@ entry:
define double @trunc_f64(double %i) nounwind {
; NOLSX-LABEL: trunc_f64:
; NOLSX: # %bb.0: # %entry
-; NOLSX-NEXT: b %plt(trunc)
+; NOLSX-NEXT: pcaddu18i $t8, %call36(trunc)
+; NOLSX-NEXT: jr $t8
;
; LSX-LABEL: trunc_f64:
; LSX: # %bb.0: # %entry
@@ -114,7 +120,8 @@ entry:
define float @roundeven_f32(float %i) nounwind {
; NOLSX-LABEL: roundeven_f32:
; NOLSX: # %bb.0: # %entry
-; NOLSX-NEXT: b %plt(roundevenf)
+; NOLSX-NEXT: pcaddu18i $t8, %call36(roundevenf)
+; NOLSX-NEXT: jr $t8
;
; LSX-LABEL: roundeven_f32:
; LSX: # %bb.0: # %entry
@@ -132,7 +139,8 @@ entry:
define double @roundeven_f64(double %i) nounwind {
; NOLSX-LABEL: roundeven_f64:
; NOLSX: # %bb.0: # %entry
-; NOLSX-NEXT: b %plt(roundeven)
+; NOLSX-NEXT: pcaddu18i $t8, %call36(roundeven)
+; NOLSX-NEXT: jr $t8
;
; LSX-LABEL: roundeven_f64:
; LSX: # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/LoongArch/fp-trunc-store.ll b/llvm/test/CodeGen/LoongArch/fp-trunc-store.ll
index 84e52d9d18c72..2db3bdb234eb0 100644
--- a/llvm/test/CodeGen/LoongArch/fp-trunc-store.ll
+++ b/llvm/test/CodeGen/LoongArch/fp-trunc-store.ll
@@ -33,7 +33,8 @@ define void @fp_trunc(ptr %a, double %b) nounwind {
; LA64F-NEXT: st.d $fp, $sp, 0 # 8-byte Folded Spill
; LA64F-NEXT: move $fp, $a0
; LA64F-NEXT: move $a0, $a1
-; LA64F-NEXT: bl %plt(__truncdfsf2)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__truncdfsf2)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: fst.s $fa0, $fp, 0
; LA64F-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/LoongArch/fp16-promote.ll b/llvm/test/CodeGen/LoongArch/fp16-promote.ll
index 3701f0df1d2b2..61a371629557e 100644
--- a/llvm/test/CodeGen/LoongArch/fp16-promote.ll
+++ b/llvm/test/CodeGen/LoongArch/fp16-promote.ll
@@ -28,7 +28,8 @@ define float @test_fpextend_float(ptr %p) nounwind {
; LA64-LABEL: test_fpextend_float:
; LA64: # %bb.0:
; LA64-NEXT: ld.hu $a0, $a0, 0
-; LA64-NEXT: b %plt(__extendhfsf2)
+; LA64-NEXT: pcaddu18i $t8, %call36(__extendhfsf2)
+; LA64-NEXT: jr $t8
%a = load half, ptr %p
%r = fpext half %a to float
ret float %r
@@ -51,7 +52,8 @@ define double @test_fpextend_double(ptr %p) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: ld.hu $a0, $a0, 0
-; LA64-NEXT: bl %plt(__extendhfsf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__extendhfsf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fcvt.d.s $fa0, $fa0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
@@ -81,7 +83,8 @@ define void @test_fptrunc_float(float %f, ptr %p) nounwind {
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: st.d $fp, $sp, 0 # 8-byte Folded Spill
; LA64-NEXT: move $fp, $a0
-; LA64-NEXT: bl %plt(__truncsfhf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__truncsfhf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: st.h $a0, $fp, 0
; LA64-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
@@ -112,7 +115,8 @@ define void @test_fptrunc_double(double %d, ptr %p) nounwind {
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: st.d $fp, $sp, 0 # 8-byte Folded Spill
; LA64-NEXT: move $fp, $a0
-; LA64-NEXT: bl %plt(__truncdfhf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__truncdfhf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: st.h $a0, $fp, 0
; LA64-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
@@ -152,12 +156,15 @@ define half @test_fadd_reg(half %a, half %b) nounwind {
; LA64-NEXT: fst.d $fs0, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: move $fp, $a0
; LA64-NEXT: move $a0, $a1
-; LA64-NEXT: bl %plt(__extendhfsf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__extendhfsf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fmov.s $fs0, $fa0
; LA64-NEXT: move $a0, $fp
-; LA64-NEXT: bl %plt(__extendhfsf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__extendhfsf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fadd.s $fa0, $fa0, $fs0
-; LA64-NEXT: bl %plt(__truncsfhf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__truncsfhf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fld.d $fs0, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: ld.d $fp, $sp, 16 # 8-byte Folded Reload
; LA64-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload
@@ -202,12 +209,15 @@ define void @test_fadd_mem(ptr %p, ptr %q) nounwind {
; LA64-NEXT: move $fp, $a0
; LA64-NEXT: ld.hu $s0, $a0, 0
; LA64-NEXT: ld.hu $a0, $a1, 0
-; LA64-NEXT: bl %plt(__extendhfsf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__extendhfsf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fmov.s $fs0, $fa0
; LA64-NEXT: move $a0, $s0
-; LA64-NEXT: bl %plt(__extendhfsf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__extendhfsf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fadd.s $fa0, $fa0, $fs0
-; LA64-NEXT: bl %plt(__truncsfhf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__truncsfhf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: st.h $a0, $fp, 0
; LA64-NEXT: fld.d $fs0, $sp, 0 # 8-byte Folded Reload
; LA64-NEXT: ld.d $s0, $sp, 8 # 8-byte Folded Reload
@@ -251,12 +261,15 @@ define half @test_fmul_reg(half %a, half %b) nounwind {
; LA64-NEXT: fst.d $fs0, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: move $fp, $a0
; LA64-NEXT: move $a0, $a1
-; LA64-NEXT: bl %plt(__extendhfsf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__extendhfsf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fmov.s $fs0, $fa0
; LA64-NEXT: move $a0, $fp
-; LA64-NEXT: bl %plt(__extendhfsf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__extendhfsf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fmul.s $fa0, $fa0, $fs0
-; LA64-NEXT: bl %plt(__truncsfhf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__truncsfhf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fld.d $fs0, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: ld.d $fp, $sp, 16 # 8-byte Folded Reload
; LA64-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload
@@ -301,12 +314,15 @@ define void @test_fmul_mem(ptr %p, ptr %q) nounwind {
; LA64-NEXT: move $fp, $a0
; LA64-NEXT: ld.hu $s0, $a0, 0
; LA64-NEXT: ld.hu $a0, $a1, 0
-; LA64-NEXT: bl %plt(__extendhfsf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__extendhfsf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fmov.s $fs0, $fa0
; LA64-NEXT: move $a0, $s0
-; LA64-NEXT: bl %plt(__extendhfsf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__extendhfsf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fmul.s $fa0, $fa0, $fs0
-; LA64-NEXT: bl %plt(__truncsfhf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__truncsfhf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: st.h $a0, $fp, 0
; LA64-NEXT: fld.d $fs0, $sp, 0 # 8-byte Folded Reload
; LA64-NEXT: ld.d $s0, $sp, 8 # 8-byte Folded Reload
@@ -340,10 +356,13 @@ define half @freeze_half_undef() nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: movgr2fr.w $fa0, $zero
-; LA64-NEXT: bl %plt(__truncsfhf2)
-; LA64-NEXT: bl %plt(__extendhfsf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__truncsfhf2)
+; LA64-NEXT: jirl $ra, $ra, 0
+; LA64-NEXT: pcaddu18i $ra, %call36(__extendhfsf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fadd.s $fa0, $fa0, $fa0
-; LA64-NEXT: bl %plt(__truncsfhf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__truncsfhf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
@@ -368,9 +387,11 @@ define half @freeze_half_poison(half %maybe.poison) nounwind {
; LA64: # %bb.0:
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(__extendhfsf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__extendhfsf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: fadd.s $fa0, $fa0, $fa0
-; LA64-NEXT: bl %plt(__truncsfhf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__truncsfhf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
@@ -395,7 +416,8 @@ define signext i32 @test_half_to_s32(half %a) nounwind {
; LA64: # %bb.0: # %entry
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(__extendhfsf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__extendhfsf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ftintrz.w.s $fa0, $fa0
; LA64-NEXT: movfr2gr.s $a0, $fa0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
@@ -422,7 +444,8 @@ define zeroext i32 @test_half_to_s32_u32(half %a) nounwind {
; LA64: # %bb.0: # %entry
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(__extendhfsf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__extendhfsf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ftintrz.w.s $fa0, $fa0
; LA64-NEXT: movfr2gr.s $a0, $fa0
; LA64-NEXT: bstrpick.d $a0, $a0, 31, 0
@@ -449,7 +472,8 @@ define i64 @test_half_to_i64(half %a) nounwind {
; LA64: # %bb.0: # %entry
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(__extendhfsf2)
+; LA64-NEXT: pcaddu18i $ra, %call36(__extendhfsf2)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ftintrz.l.s $fa0, $fa0
; LA64-NEXT: movfr2gr.d $a0, $fa0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/LoongArch/frame.ll b/llvm/test/CodeGen/LoongArch/frame.ll
index cf15fd8bdb437..048703029d8c6 100644
--- a/llvm/test/CodeGen/LoongArch/frame.ll
+++ b/llvm/test/CodeGen/LoongArch/frame.ll
@@ -15,7 +15,8 @@ define i32 @test() nounwind {
; CHECK-NEXT: vrepli.b $vr0, 0
; CHECK-NEXT: vst $vr0, $sp, 0
; CHECK-NEXT: addi.d $a0, $sp, 4
-; CHECK-NEXT: bl %plt(test1)
+; CHECK-NEXT: pcaddu18i $ra, %call36(test1)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: move $a0, $zero
; CHECK-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 32
diff --git a/llvm/test/CodeGen/LoongArch/frint.ll b/llvm/test/CodeGen/LoongArch/frint.ll
index 30718f7c7fa3e..48b1ff86ecf9c 100644
--- a/llvm/test/CodeGen/LoongArch/frint.ll
+++ b/llvm/test/CodeGen/LoongArch/frint.ll
@@ -47,7 +47,8 @@ define double @rint_f64(double %d) nounwind {
; LA64F: # %bb.0: # %entry
; LA64F-NEXT: addi.d $sp, $sp, -16
; LA64F-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64F-NEXT: bl %plt(rint)
+; LA64F-NEXT: pcaddu18i $ra, %call36(rint)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64F-NEXT: addi.d $sp, $sp, 16
; LA64F-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/fsqrt.ll b/llvm/test/CodeGen/LoongArch/fsqrt.ll
index 776de7f729ec4..c5f02ba53039a 100644
--- a/llvm/test/CodeGen/LoongArch/fsqrt.ll
+++ b/llvm/test/CodeGen/LoongArch/fsqrt.ll
@@ -50,7 +50,8 @@ define double @fsqrt_f64(double %a) nounwind {
; LA64F: # %bb.0:
; LA64F-NEXT: addi.d $sp, $sp, -16
; LA64F-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64F-NEXT: bl %plt(sqrt)
+; LA64F-NEXT: pcaddu18i $ra, %call36(sqrt)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64F-NEXT: addi.d $sp, $sp, 16
; LA64F-NEXT: ret
@@ -112,10 +113,12 @@ define double @frsqrt_f64(double %a) nounwind {
; LA64F: # %bb.0:
; LA64F-NEXT: addi.d $sp, $sp, -16
; LA64F-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64F-NEXT: bl %plt(sqrt)
+; LA64F-NEXT: pcaddu18i $ra, %call36(sqrt)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: move $a1, $a0
; LA64F-NEXT: lu52i.d $a0, $zero, 1023
-; LA64F-NEXT: bl %plt(__divdf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__divdf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64F-NEXT: addi.d $sp, $sp, 16
; LA64F-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/ghc-cc.ll b/llvm/test/CodeGen/LoongArch/ghc-cc.ll
index f99759b4b5ed5..1b7e8cf7bfba1 100644
--- a/llvm/test/CodeGen/LoongArch/ghc-cc.ll
+++ b/llvm/test/CodeGen/LoongArch/ghc-cc.ll
@@ -60,7 +60,8 @@ define ghccc void @foo() nounwind {
; LA64-NEXT: ld.d $s1, $a0, %pc_lo12(sp)
; LA64-NEXT: pcalau12i $a0, %pc_hi20(base)
; LA64-NEXT: ld.d $s0, $a0, %pc_lo12(base)
-; LA64-NEXT: b %plt(bar)
+; LA64-NEXT: pcaddu18i $t8, %call36(bar)
+; LA64-NEXT: jr $t8
entry:
%0 = load double, ptr @d4
diff --git a/llvm/test/CodeGen/LoongArch/intrinsic-csr-side-effects.ll b/llvm/test/CodeGen/LoongArch/intrinsic-csr-side-effects.ll
index d14483939fbd1..c2f77b0a8a70e 100644
--- a/llvm/test/CodeGen/LoongArch/intrinsic-csr-side-effects.ll
+++ b/llvm/test/CodeGen/LoongArch/intrinsic-csr-side-effects.ll
@@ -1,27 +1,44 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch32 -mattr=+d < %s | FileCheck %s
-; RUN: llc --mtriple=loongarch64 -mattr=+d < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 -mattr=+d < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 -mattr=+d < %s | FileCheck %s --check-prefix=LA64
declare i32 @llvm.loongarch.csrrd.w(i32 immarg) nounwind
declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg) nounwind
declare void @bug()
define dso_local void @foo(i32 noundef signext %flag) nounwind {
-; CHECK-LABEL: foo:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: beqz $a0, .LBB0_2
-; CHECK-NEXT: # %bb.1: # %if.then
-; CHECK-NEXT: csrrd $a0, 2
-; CHECK-NEXT: ori $a0, $a0, 1
-; CHECK-NEXT: csrwr $a0, 2
-; CHECK-NEXT: .LBB0_2: # %if.end
-; CHECK-NEXT: csrrd $a0, 2
-; CHECK-NEXT: andi $a0, $a0, 1
-; CHECK-NEXT: bnez $a0, .LBB0_4
-; CHECK-NEXT: # %bb.3: # %if.then2
-; CHECK-NEXT: b %plt(bug)
-; CHECK-NEXT: .LBB0_4: # %if.end3
-; CHECK-NEXT: ret
+; LA32-LABEL: foo:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: beqz $a0, .LBB0_2
+; LA32-NEXT: # %bb.1: # %if.then
+; LA32-NEXT: csrrd $a0, 2
+; LA32-NEXT: ori $a0, $a0, 1
+; LA32-NEXT: csrwr $a0, 2
+; LA32-NEXT: .LBB0_2: # %if.end
+; LA32-NEXT: csrrd $a0, 2
+; LA32-NEXT: andi $a0, $a0, 1
+; LA32-NEXT: bnez $a0, .LBB0_4
+; LA32-NEXT: # %bb.3: # %if.then2
+; LA32-NEXT: b %plt(bug)
+; LA32-NEXT: .LBB0_4: # %if.end3
+; LA32-NEXT: ret
+;
+; LA64-LABEL: foo:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: beqz $a0, .LBB0_2
+; LA64-NEXT: # %bb.1: # %if.then
+; LA64-NEXT: csrrd $a0, 2
+; LA64-NEXT: ori $a0, $a0, 1
+; LA64-NEXT: csrwr $a0, 2
+; LA64-NEXT: .LBB0_2: # %if.end
+; LA64-NEXT: csrrd $a0, 2
+; LA64-NEXT: andi $a0, $a0, 1
+; LA64-NEXT: bnez $a0, .LBB0_4
+; LA64-NEXT: # %bb.3: # %if.then2
+; LA64-NEXT: pcaddu18i $t8, %call36(bug)
+; LA64-NEXT: jr $t8
+; LA64-NEXT: .LBB0_4: # %if.end3
+; LA64-NEXT: ret
entry:
%tobool.not = icmp eq i32 %flag, 0
br i1 %tobool.not, label %if.end, label %if.then
diff --git a/llvm/test/CodeGen/LoongArch/intrinsic-iocsr-side-effects.ll b/llvm/test/CodeGen/LoongArch/intrinsic-iocsr-side-effects.ll
index e2a1f8a7ccd09..222eae850c4af 100644
--- a/llvm/test/CodeGen/LoongArch/intrinsic-iocsr-side-effects.ll
+++ b/llvm/test/CodeGen/LoongArch/intrinsic-iocsr-side-effects.ll
@@ -26,7 +26,8 @@ define dso_local void @test_b(i32 noundef signext %flag) nounwind {
; CHECK-NEXT: andi $a0, $a0, 1
; CHECK-NEXT: bnez $a0, .LBB0_4
; CHECK-NEXT: # %bb.3: # %if.then2
-; CHECK-NEXT: b %plt(bug)
+; CHECK-NEXT: pcaddu18i $t8, %call36(bug)
+; CHECK-NEXT: jr $t8
; CHECK-NEXT: .LBB0_4: # %if.end3
; CHECK-NEXT: ret
entry:
@@ -68,7 +69,8 @@ define dso_local void @test_h(i32 noundef signext %flag) nounwind {
; CHECK-NEXT: andi $a0, $a0, 1
; CHECK-NEXT: bnez $a0, .LBB1_4
; CHECK-NEXT: # %bb.3: # %if.then2
-; CHECK-NEXT: b %plt(bug)
+; CHECK-NEXT: pcaddu18i $t8, %call36(bug)
+; CHECK-NEXT: jr $t8
; CHECK-NEXT: .LBB1_4: # %if.end3
; CHECK-NEXT: ret
entry:
@@ -110,7 +112,8 @@ define dso_local void @test_w(i32 noundef signext %flag) nounwind {
; CHECK-NEXT: andi $a0, $a0, 1
; CHECK-NEXT: bnez $a0, .LBB2_4
; CHECK-NEXT: # %bb.3: # %if.then2
-; CHECK-NEXT: b %plt(bug)
+; CHECK-NEXT: pcaddu18i $t8, %call36(bug)
+; CHECK-NEXT: jr $t8
; CHECK-NEXT: .LBB2_4: # %if.end3
; CHECK-NEXT: ret
entry:
@@ -152,7 +155,8 @@ define dso_local void @test_d(i32 noundef signext %flag) nounwind {
; CHECK-NEXT: andi $a0, $a0, 1
; CHECK-NEXT: bnez $a0, .LBB3_4
; CHECK-NEXT: # %bb.3: # %if.then2
-; CHECK-NEXT: b %plt(bug)
+; CHECK-NEXT: pcaddu18i $t8, %call36(bug)
+; CHECK-NEXT: jr $t8
; CHECK-NEXT: .LBB3_4: # %if.end3
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg-128.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg-128.ll
index b731081386a2c..e8be3d80716de 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg-128.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg-128.ll
@@ -16,7 +16,8 @@ define void @cmpxchg_i128_acquire_acquire(ptr %ptr, i128 %cmp, i128 %val) nounwi
; LA64-NEXT: ori $a5, $zero, 2
; LA64-NEXT: move $a2, $a3
; LA64-NEXT: move $a3, $a6
-; LA64-NEXT: bl %plt(__atomic_compare_exchange_16)
+; LA64-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange_16)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 32
; LA64-NEXT: ret
@@ -55,7 +56,8 @@ define void @cmpxchg_i128_acquire_monotonic(ptr %ptr, i128 %cmp, i128 %val) noun
; LA64-NEXT: move $a2, $a3
; LA64-NEXT: move $a3, $a5
; LA64-NEXT: move $a5, $zero
-; LA64-NEXT: bl %plt(__atomic_compare_exchange_16)
+; LA64-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange_16)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 32
; LA64-NEXT: ret
@@ -94,7 +96,8 @@ define i128 @cmpxchg_i128_acquire_acquire_reti128(ptr %ptr, i128 %cmp, i128 %val
; LA64-NEXT: ori $a5, $zero, 2
; LA64-NEXT: move $a2, $a3
; LA64-NEXT: move $a3, $a6
-; LA64-NEXT: bl %plt(__atomic_compare_exchange_16)
+; LA64-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange_16)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $a1, $sp, 8
; LA64-NEXT: ld.d $a0, $sp, 0
; LA64-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload
@@ -138,7 +141,8 @@ define i1 @cmpxchg_i128_acquire_acquire_reti1(ptr %ptr, i128 %cmp, i128 %val) no
; LA64-NEXT: ori $a5, $zero, 2
; LA64-NEXT: move $a2, $a3
; LA64-NEXT: move $a3, $a6
-; LA64-NEXT: bl %plt(__atomic_compare_exchange_16)
+; LA64-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange_16)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 32
; LA64-NEXT: ret
@@ -182,7 +186,8 @@ define void @cmpxchg_i128_monotonic_monotonic(ptr %ptr, i128 %cmp, i128 %val) no
; LA64-NEXT: move $a3, $a4
; LA64-NEXT: move $a4, $zero
; LA64-NEXT: move $a5, $zero
-; LA64-NEXT: bl %plt(__atomic_compare_exchange_16)
+; LA64-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange_16)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 32
; LA64-NEXT: ret
@@ -237,7 +242,8 @@ define i128 @cmpxchg_i128_monotonic_monotonic_reti128(ptr %ptr, i128 %cmp, i128
; LA64-NEXT: move $a3, $a4
; LA64-NEXT: move $a4, $zero
; LA64-NEXT: move $a5, $zero
-; LA64-NEXT: bl %plt(__atomic_compare_exchange_16)
+; LA64-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange_16)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $a1, $sp, 8
; LA64-NEXT: ld.d $a0, $sp, 0
; LA64-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload
@@ -299,7 +305,8 @@ define i1 @cmpxchg_i128_monotonic_monotonic_reti1(ptr %ptr, i128 %cmp, i128 %val
; LA64-NEXT: move $a3, $a4
; LA64-NEXT: move $a4, $zero
; LA64-NEXT: move $a5, $zero
-; LA64-NEXT: bl %plt(__atomic_compare_exchange_16)
+; LA64-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange_16)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 32
; LA64-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-fp.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-fp.ll
index 6ea658acdd717..caded4bd5e181 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-fp.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-fp.ll
@@ -301,7 +301,8 @@ define double @double_fadd_acquire(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -310,7 +311,8 @@ define double @double_fadd_acquire(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 2
; LA64F-NEXT: ori $a5, $zero, 2
; LA64F-NEXT: move $a1, $fp
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB4_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -342,7 +344,8 @@ define double @double_fadd_acquire(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 2
; LA64D-NEXT: ori $a5, $zero, 2
; LA64D-NEXT: move $a1, $fp
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB4_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -370,7 +373,8 @@ define double @double_fsub_acquire(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -379,7 +383,8 @@ define double @double_fsub_acquire(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 2
; LA64F-NEXT: ori $a5, $zero, 2
; LA64F-NEXT: move $a1, $fp
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB5_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -411,7 +416,8 @@ define double @double_fsub_acquire(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 2
; LA64D-NEXT: ori $a5, $zero, 2
; LA64D-NEXT: move $a1, $fp
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB5_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -439,7 +445,8 @@ define double @double_fmin_acquire(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(fmin)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fmin)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -448,7 +455,8 @@ define double @double_fmin_acquire(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 2
; LA64F-NEXT: ori $a5, $zero, 2
; LA64F-NEXT: move $a1, $fp
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB6_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -481,7 +489,8 @@ define double @double_fmin_acquire(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 2
; LA64D-NEXT: ori $a5, $zero, 2
; LA64D-NEXT: move $a1, $fp
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB6_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -509,7 +518,8 @@ define double @double_fmax_acquire(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(fmax)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fmax)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -518,7 +528,8 @@ define double @double_fmax_acquire(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 2
; LA64F-NEXT: ori $a5, $zero, 2
; LA64F-NEXT: move $a1, $fp
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB7_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -551,7 +562,8 @@ define double @double_fmax_acquire(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 2
; LA64D-NEXT: ori $a5, $zero, 2
; LA64D-NEXT: move $a1, $fp
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB7_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -862,7 +874,8 @@ define double @double_fadd_release(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -871,7 +884,8 @@ define double @double_fadd_release(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 3
; LA64F-NEXT: move $a1, $fp
; LA64F-NEXT: move $a5, $zero
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB12_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -903,7 +917,8 @@ define double @double_fadd_release(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 3
; LA64D-NEXT: move $a1, $fp
; LA64D-NEXT: move $a5, $zero
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB12_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -931,7 +946,8 @@ define double @double_fsub_release(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -940,7 +956,8 @@ define double @double_fsub_release(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 3
; LA64F-NEXT: move $a1, $fp
; LA64F-NEXT: move $a5, $zero
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB13_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -972,7 +989,8 @@ define double @double_fsub_release(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 3
; LA64D-NEXT: move $a1, $fp
; LA64D-NEXT: move $a5, $zero
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB13_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -1000,7 +1018,8 @@ define double @double_fmin_release(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(fmin)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fmin)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -1009,7 +1028,8 @@ define double @double_fmin_release(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 3
; LA64F-NEXT: move $a1, $fp
; LA64F-NEXT: move $a5, $zero
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB14_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -1042,7 +1062,8 @@ define double @double_fmin_release(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 3
; LA64D-NEXT: move $a1, $fp
; LA64D-NEXT: move $a5, $zero
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB14_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -1070,7 +1091,8 @@ define double @double_fmax_release(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(fmax)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fmax)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -1079,7 +1101,8 @@ define double @double_fmax_release(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 3
; LA64F-NEXT: move $a1, $fp
; LA64F-NEXT: move $a5, $zero
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB15_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -1112,7 +1135,8 @@ define double @double_fmax_release(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 3
; LA64D-NEXT: move $a1, $fp
; LA64D-NEXT: move $a5, $zero
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB15_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -1423,7 +1447,8 @@ define double @double_fadd_acq_rel(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -1432,7 +1457,8 @@ define double @double_fadd_acq_rel(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 4
; LA64F-NEXT: ori $a5, $zero, 2
; LA64F-NEXT: move $a1, $fp
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB20_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -1464,7 +1490,8 @@ define double @double_fadd_acq_rel(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 4
; LA64D-NEXT: ori $a5, $zero, 2
; LA64D-NEXT: move $a1, $fp
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB20_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -1492,7 +1519,8 @@ define double @double_fsub_acq_rel(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -1501,7 +1529,8 @@ define double @double_fsub_acq_rel(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 4
; LA64F-NEXT: ori $a5, $zero, 2
; LA64F-NEXT: move $a1, $fp
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB21_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -1533,7 +1562,8 @@ define double @double_fsub_acq_rel(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 4
; LA64D-NEXT: ori $a5, $zero, 2
; LA64D-NEXT: move $a1, $fp
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB21_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -1561,7 +1591,8 @@ define double @double_fmin_acq_rel(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(fmin)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fmin)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -1570,7 +1601,8 @@ define double @double_fmin_acq_rel(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 4
; LA64F-NEXT: ori $a5, $zero, 2
; LA64F-NEXT: move $a1, $fp
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB22_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -1603,7 +1635,8 @@ define double @double_fmin_acq_rel(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 4
; LA64D-NEXT: ori $a5, $zero, 2
; LA64D-NEXT: move $a1, $fp
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB22_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -1631,7 +1664,8 @@ define double @double_fmax_acq_rel(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(fmax)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fmax)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -1640,7 +1674,8 @@ define double @double_fmax_acq_rel(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 4
; LA64F-NEXT: ori $a5, $zero, 2
; LA64F-NEXT: move $a1, $fp
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB23_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -1673,7 +1708,8 @@ define double @double_fmax_acq_rel(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 4
; LA64D-NEXT: ori $a5, $zero, 2
; LA64D-NEXT: move $a1, $fp
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB23_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -1984,7 +2020,8 @@ define double @double_fadd_seq_cst(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -1993,7 +2030,8 @@ define double @double_fadd_seq_cst(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 5
; LA64F-NEXT: ori $a5, $zero, 5
; LA64F-NEXT: move $a1, $fp
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB28_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -2025,7 +2063,8 @@ define double @double_fadd_seq_cst(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 5
; LA64D-NEXT: ori $a5, $zero, 5
; LA64D-NEXT: move $a1, $fp
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB28_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -2053,7 +2092,8 @@ define double @double_fsub_seq_cst(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -2062,7 +2102,8 @@ define double @double_fsub_seq_cst(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 5
; LA64F-NEXT: ori $a5, $zero, 5
; LA64F-NEXT: move $a1, $fp
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB29_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -2094,7 +2135,8 @@ define double @double_fsub_seq_cst(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 5
; LA64D-NEXT: ori $a5, $zero, 5
; LA64D-NEXT: move $a1, $fp
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB29_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -2122,7 +2164,8 @@ define double @double_fmin_seq_cst(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(fmin)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fmin)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -2131,7 +2174,8 @@ define double @double_fmin_seq_cst(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 5
; LA64F-NEXT: ori $a5, $zero, 5
; LA64F-NEXT: move $a1, $fp
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB30_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -2164,7 +2208,8 @@ define double @double_fmin_seq_cst(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 5
; LA64D-NEXT: ori $a5, $zero, 5
; LA64D-NEXT: move $a1, $fp
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB30_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -2192,7 +2237,8 @@ define double @double_fmax_seq_cst(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(fmax)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fmax)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -2201,7 +2247,8 @@ define double @double_fmax_seq_cst(ptr %p) nounwind {
; LA64F-NEXT: ori $a4, $zero, 5
; LA64F-NEXT: ori $a5, $zero, 5
; LA64F-NEXT: move $a1, $fp
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB31_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -2234,7 +2281,8 @@ define double @double_fmax_seq_cst(ptr %p) nounwind {
; LA64D-NEXT: ori $a4, $zero, 5
; LA64D-NEXT: ori $a5, $zero, 5
; LA64D-NEXT: move $a1, $fp
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB31_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -2545,7 +2593,8 @@ define double @double_fadd_monotonic(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -2554,7 +2603,8 @@ define double @double_fadd_monotonic(ptr %p) nounwind {
; LA64F-NEXT: move $a1, $fp
; LA64F-NEXT: move $a4, $zero
; LA64F-NEXT: move $a5, $zero
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB36_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -2586,7 +2636,8 @@ define double @double_fadd_monotonic(ptr %p) nounwind {
; LA64D-NEXT: move $a1, $fp
; LA64D-NEXT: move $a4, $zero
; LA64D-NEXT: move $a5, $zero
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB36_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -2614,7 +2665,8 @@ define double @double_fsub_monotonic(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -2623,7 +2675,8 @@ define double @double_fsub_monotonic(ptr %p) nounwind {
; LA64F-NEXT: move $a1, $fp
; LA64F-NEXT: move $a4, $zero
; LA64F-NEXT: move $a5, $zero
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB37_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -2655,7 +2708,8 @@ define double @double_fsub_monotonic(ptr %p) nounwind {
; LA64D-NEXT: move $a1, $fp
; LA64D-NEXT: move $a4, $zero
; LA64D-NEXT: move $a5, $zero
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB37_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -2683,7 +2737,8 @@ define double @double_fmin_monotonic(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(fmin)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fmin)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -2692,7 +2747,8 @@ define double @double_fmin_monotonic(ptr %p) nounwind {
; LA64F-NEXT: move $a1, $fp
; LA64F-NEXT: move $a4, $zero
; LA64F-NEXT: move $a5, $zero
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB38_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -2725,7 +2781,8 @@ define double @double_fmin_monotonic(ptr %p) nounwind {
; LA64D-NEXT: move $a1, $fp
; LA64D-NEXT: move $a4, $zero
; LA64D-NEXT: move $a5, $zero
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB38_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
@@ -2753,7 +2810,8 @@ define double @double_fmax_monotonic(ptr %p) nounwind {
; LA64F-NEXT: # =>This Inner Loop Header: Depth=1
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(fmax)
+; LA64F-NEXT: pcaddu18i $ra, %call36(fmax)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $s1, $sp, 8
; LA64F-NEXT: st.d $a0, $sp, 0
; LA64F-NEXT: ori $a0, $zero, 8
@@ -2762,7 +2820,8 @@ define double @double_fmax_monotonic(ptr %p) nounwind {
; LA64F-NEXT: move $a1, $fp
; LA64F-NEXT: move $a4, $zero
; LA64F-NEXT: move $a5, $zero
-; LA64F-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $s1, $sp, 8
; LA64F-NEXT: beqz $a0, .LBB39_1
; LA64F-NEXT: # %bb.2: # %atomicrmw.end
@@ -2795,7 +2854,8 @@ define double @double_fmax_monotonic(ptr %p) nounwind {
; LA64D-NEXT: move $a1, $fp
; LA64D-NEXT: move $a4, $zero
; LA64D-NEXT: move $a5, $zero
-; LA64D-NEXT: bl %plt(__atomic_compare_exchange)
+; LA64D-NEXT: pcaddu18i $ra, %call36(__atomic_compare_exchange)
+; LA64D-NEXT: jirl $ra, $ra, 0
; LA64D-NEXT: fld.d $fa0, $sp, 8
; LA64D-NEXT: beqz $a0, .LBB39_1
; LA64D-NEXT: # %bb.2: # %atomicrmw.end
diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/call.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/call.ll
index e2d1c556aaf9a..653af9f490905 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/call.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/call.ll
@@ -18,7 +18,8 @@ define i32 @test_call_external(i32 %a) nounwind {
; LA64: # %bb.0:
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(external_function)
+; LA64-NEXT: pcaddu18i $ra, %call36(external_function)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
@@ -54,7 +55,8 @@ define i32 @test_call_defined(i32 %a) nounwind {
; LA64: # %bb.0:
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(defined_function)
+; LA64-NEXT: pcaddu18i $ra, %call36(defined_function)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll
index b7de5a592c359..e4cfd7a5fec30 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/float-convert.ll
@@ -407,7 +407,8 @@ define float @convert_i64_to_float(i64 %a) nounwind {
; LA64F: # %bb.0:
; LA64F-NEXT: addi.d $sp, $sp, -16
; LA64F-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64F-NEXT: bl %plt(__floatdisf)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__floatdisf)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64F-NEXT: addi.d $sp, $sp, 16
; LA64F-NEXT: ret
@@ -512,7 +513,8 @@ define float @convert_u32_to_float(i32 %a) nounwind {
; LA64F-NEXT: addi.d $sp, $sp, -16
; LA64F-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64F-NEXT: bstrpick.d $a0, $a0, 31, 0
-; LA64F-NEXT: bl %plt(__floatundisf)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__floatundisf)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64F-NEXT: addi.d $sp, $sp, 16
; LA64F-NEXT: ret
@@ -550,7 +552,8 @@ define float @convert_u64_to_float(i64 %a) nounwind {
; LA64F: # %bb.0:
; LA64F-NEXT: addi.d $sp, $sp, -16
; LA64F-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64F-NEXT: bl %plt(__floatundisf)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__floatundisf)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64F-NEXT: addi.d $sp, $sp, 16
; LA64F-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/lasx/fpowi.ll b/llvm/test/CodeGen/LoongArch/lasx/fpowi.ll
index f6b14a9bb000f..789b51d9b5e5b 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/fpowi.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/fpowi.ll
@@ -14,7 +14,8 @@ define <8 x float> @powi_v8f32(<8 x float> %va, i32 %b) nounwind {
; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 0
; CHECK-NEXT: movgr2fr.w $fa0, $a0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powisf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 0
; CHECK-NEXT: xvst $xr0, $sp, 32 # 32-byte Folded Spill
@@ -22,7 +23,8 @@ define <8 x float> @powi_v8f32(<8 x float> %va, i32 %b) nounwind {
; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 1
; CHECK-NEXT: movgr2fr.w $fa0, $a0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powisf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
; CHECK-NEXT: xvld $xr0, $sp, 32 # 32-byte Folded Reload
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 1
@@ -31,7 +33,8 @@ define <8 x float> @powi_v8f32(<8 x float> %va, i32 %b) nounwind {
; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 2
; CHECK-NEXT: movgr2fr.w $fa0, $a0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powisf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
; CHECK-NEXT: xvld $xr0, $sp, 32 # 32-byte Folded Reload
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 2
@@ -40,7 +43,8 @@ define <8 x float> @powi_v8f32(<8 x float> %va, i32 %b) nounwind {
; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 3
; CHECK-NEXT: movgr2fr.w $fa0, $a0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powisf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
; CHECK-NEXT: xvld $xr0, $sp, 32 # 32-byte Folded Reload
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 3
@@ -49,7 +53,8 @@ define <8 x float> @powi_v8f32(<8 x float> %va, i32 %b) nounwind {
; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 4
; CHECK-NEXT: movgr2fr.w $fa0, $a0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powisf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
; CHECK-NEXT: xvld $xr0, $sp, 32 # 32-byte Folded Reload
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 4
@@ -58,7 +63,8 @@ define <8 x float> @powi_v8f32(<8 x float> %va, i32 %b) nounwind {
; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 5
; CHECK-NEXT: movgr2fr.w $fa0, $a0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powisf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
; CHECK-NEXT: xvld $xr0, $sp, 32 # 32-byte Folded Reload
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 5
@@ -67,7 +73,8 @@ define <8 x float> @powi_v8f32(<8 x float> %va, i32 %b) nounwind {
; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 6
; CHECK-NEXT: movgr2fr.w $fa0, $a0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powisf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
; CHECK-NEXT: xvld $xr0, $sp, 32 # 32-byte Folded Reload
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 6
@@ -76,7 +83,8 @@ define <8 x float> @powi_v8f32(<8 x float> %va, i32 %b) nounwind {
; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 7
; CHECK-NEXT: movgr2fr.w $fa0, $a0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powisf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
; CHECK-NEXT: xvld $xr0, $sp, 32 # 32-byte Folded Reload
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 7
@@ -102,7 +110,8 @@ define <4 x double> @powi_v4f64(<4 x double> %va, i32 %b) nounwind {
; CHECK-NEXT: xvpickve2gr.d $a0, $xr0, 0
; CHECK-NEXT: movgr2fr.d $fa0, $a0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powidf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powidf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.d $a0, $fa0
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 0
; CHECK-NEXT: xvst $xr0, $sp, 32 # 32-byte Folded Spill
@@ -110,7 +119,8 @@ define <4 x double> @powi_v4f64(<4 x double> %va, i32 %b) nounwind {
; CHECK-NEXT: xvpickve2gr.d $a0, $xr0, 1
; CHECK-NEXT: movgr2fr.d $fa0, $a0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powidf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powidf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.d $a0, $fa0
; CHECK-NEXT: xvld $xr0, $sp, 32 # 32-byte Folded Reload
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 1
@@ -119,7 +129,8 @@ define <4 x double> @powi_v4f64(<4 x double> %va, i32 %b) nounwind {
; CHECK-NEXT: xvpickve2gr.d $a0, $xr0, 2
; CHECK-NEXT: movgr2fr.d $fa0, $a0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powidf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powidf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.d $a0, $fa0
; CHECK-NEXT: xvld $xr0, $sp, 32 # 32-byte Folded Reload
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 2
@@ -128,7 +139,8 @@ define <4 x double> @powi_v4f64(<4 x double> %va, i32 %b) nounwind {
; CHECK-NEXT: xvpickve2gr.d $a0, $xr0, 3
; CHECK-NEXT: movgr2fr.d $fa0, $a0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powidf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powidf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.d $a0, $fa0
; CHECK-NEXT: xvld $xr0, $sp, 32 # 32-byte Folded Reload
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 3
diff --git a/llvm/test/CodeGen/LoongArch/libcall-extend.ll b/llvm/test/CodeGen/LoongArch/libcall-extend.ll
index 7ca69811a7d57..8f94462858cf0 100644
--- a/llvm/test/CodeGen/LoongArch/libcall-extend.ll
+++ b/llvm/test/CodeGen/LoongArch/libcall-extend.ll
@@ -7,7 +7,8 @@ define signext i32 @convert_float_to_i32(i32 %tmp, float %a) nounwind {
; CHECK-NEXT: addi.d $sp, $sp, -16
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; CHECK-NEXT: move $a0, $a1
-; CHECK-NEXT: bl %plt(__fixsfsi)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__fixsfsi)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
@@ -21,7 +22,8 @@ define signext i32 @convert_double_to_i32(i32 %tmp, double %a) nounwind {
; CHECK-NEXT: addi.d $sp, $sp, -16
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; CHECK-NEXT: move $a0, $a1
-; CHECK-NEXT: bl %plt(__fixdfsi)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__fixdfsi)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
@@ -36,7 +38,8 @@ define signext i32 @convert_fp128_to_i32(i32 %tmp, fp128 %a) nounwind {
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; CHECK-NEXT: move $a0, $a1
; CHECK-NEXT: move $a1, $a2
-; CHECK-NEXT: bl %plt(__fixtfsi)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__fixtfsi)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/lsx/fpowi.ll b/llvm/test/CodeGen/LoongArch/lsx/fpowi.ll
index b0f54e78c7a44..aafef07fbb8f4 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/fpowi.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/fpowi.ll
@@ -14,7 +14,8 @@ define <4 x float> @powi_v4f32(<4 x float> %va, i32 %b) nounwind {
; CHECK-NEXT: vreplvei.w $vr0, $vr0, 0
; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powisf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
; CHECK-NEXT: vst $vr0, $sp, 16 # 16-byte Folded Spill
@@ -22,7 +23,8 @@ define <4 x float> @powi_v4f32(<4 x float> %va, i32 %b) nounwind {
; CHECK-NEXT: vreplvei.w $vr0, $vr0, 1
; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powisf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
; CHECK-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 1
@@ -31,7 +33,8 @@ define <4 x float> @powi_v4f32(<4 x float> %va, i32 %b) nounwind {
; CHECK-NEXT: vreplvei.w $vr0, $vr0, 2
; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powisf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
; CHECK-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 2
@@ -40,7 +43,8 @@ define <4 x float> @powi_v4f32(<4 x float> %va, i32 %b) nounwind {
; CHECK-NEXT: vreplvei.w $vr0, $vr0, 3
; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powisf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
; CHECK-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 3
@@ -66,7 +70,8 @@ define <2 x double> @powi_v2f64(<2 x double> %va, i32 %b) nounwind {
; CHECK-NEXT: vreplvei.d $vr0, $vr0, 0
; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powidf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powidf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.d $a0, $fa0
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
; CHECK-NEXT: vst $vr0, $sp, 16 # 16-byte Folded Spill
@@ -74,7 +79,8 @@ define <2 x double> @powi_v2f64(<2 x double> %va, i32 %b) nounwind {
; CHECK-NEXT: vreplvei.d $vr0, $vr0, 1
; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0
; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: bl %plt(__powidf2)
+; CHECK-NEXT: pcaddu18i $ra, %call36(__powidf2)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: movfr2gr.d $a0, $fa0
; CHECK-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 1
diff --git a/llvm/test/CodeGen/LoongArch/machinelicm-address-pseudos.ll b/llvm/test/CodeGen/LoongArch/machinelicm-address-pseudos.ll
index 92d079ab3a8d8..0f9275fda34ba 100644
--- a/llvm/test/CodeGen/LoongArch/machinelicm-address-pseudos.ll
+++ b/llvm/test/CodeGen/LoongArch/machinelicm-address-pseudos.ll
@@ -244,7 +244,8 @@ define void @test_la_tls_ld(i32 signext %n) {
; LA64-NEXT: .LBB3_1: # %loop
; LA64-NEXT: # =>This Inner Loop Header: Depth=1
; LA64-NEXT: move $a0, $s0
-; LA64-NEXT: bl %plt(__tls_get_addr)
+; LA64-NEXT: pcaddu18i $ra, %call36(__tls_get_addr)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.w $zero, $a0, 0
; LA64-NEXT: addi.w $s1, $s1, 1
; LA64-NEXT: blt $s1, $fp, .LBB3_1
@@ -414,7 +415,8 @@ define void @test_la_tls_gd(i32 signext %n) nounwind {
; LA64-NEXT: .LBB5_1: # %loop
; LA64-NEXT: # =>This Inner Loop Header: Depth=1
; LA64-NEXT: move $a0, $s0
-; LA64-NEXT: bl %plt(__tls_get_addr)
+; LA64-NEXT: pcaddu18i $ra, %call36(__tls_get_addr)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.w $zero, $a0, 0
; LA64-NEXT: addi.w $s1, $s1, 1
; LA64-NEXT: blt $s1, $fp, .LBB5_1
diff --git a/llvm/test/CodeGen/LoongArch/memcmp.ll b/llvm/test/CodeGen/LoongArch/memcmp.ll
index d8e322b3afe4e..c4aaf9a75a852 100644
--- a/llvm/test/CodeGen/LoongArch/memcmp.ll
+++ b/llvm/test/CodeGen/LoongArch/memcmp.ll
@@ -12,7 +12,8 @@ define signext i32 @test1(ptr %buffer1, ptr %buffer2) {
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset 1, -8
; CHECK-NEXT: ori $a2, $zero, 16
-; CHECK-NEXT: bl %plt(memcmp)
+; CHECK-NEXT: pcaddu18i $ra, %call36(memcmp)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/naked-fn-with-frame-pointer.ll b/llvm/test/CodeGen/LoongArch/naked-fn-with-frame-pointer.ll
index 9bb449101683d..9a59fa3013787 100644
--- a/llvm/test/CodeGen/LoongArch/naked-fn-with-frame-pointer.ll
+++ b/llvm/test/CodeGen/LoongArch/naked-fn-with-frame-pointer.ll
@@ -11,7 +11,8 @@ define dso_local void @naked() naked "frame-pointer"="all" {
;
; CHECK-64-LABEL: naked:
; CHECK-64: # %bb.0:
-; CHECK-64-NEXT: bl main
+; CHECK-64-NEXT: pcaddu18i $ra, %call36(main)
+; CHECK-64-NEXT: jirl $ra, $ra, 0
call void @main()
unreachable
}
@@ -39,7 +40,8 @@ define dso_local void @normal() "frame-pointer"="all" {
; CHECK-64-NEXT: .cfi_offset 22, -16
; CHECK-64-NEXT: addi.d $fp, $sp, 16
; CHECK-64-NEXT: .cfi_def_cfa 22, 0
-; CHECK-64-NEXT: bl main
+; CHECK-64-NEXT: pcaddu18i $ra, %call36(main)
+; CHECK-64-NEXT: jirl $ra, $ra, 0
call void @main()
unreachable
}
diff --git a/llvm/test/CodeGen/LoongArch/nomerge.ll b/llvm/test/CodeGen/LoongArch/nomerge.ll
index d35d3186b031e..c781d1d566b6c 100644
--- a/llvm/test/CodeGen/LoongArch/nomerge.ll
+++ b/llvm/test/CodeGen/LoongArch/nomerge.ll
@@ -13,14 +13,17 @@ define void @foo(i32 %i) nounwind {
; CHECK-NEXT: ori $a1, $zero, 5
; CHECK-NEXT: bne $a0, $a1, .LBB0_4
; CHECK-NEXT: # %bb.2: # %if.then
-; CHECK-NEXT: bl %plt(bar)
+; CHECK-NEXT: pcaddu18i $ra, %call36(bar)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: b .LBB0_4
; CHECK-NEXT: .LBB0_3: # %if.then2
-; CHECK-NEXT: bl %plt(bar)
+; CHECK-NEXT: pcaddu18i $ra, %call36(bar)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: .LBB0_4: # %if.end3
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
-; CHECK-NEXT: b %plt(bar)
+; CHECK-NEXT: pcaddu18i $t8, %call36(bar)
+; CHECK-NEXT: jr $t8
entry:
switch i32 %i, label %if.end3 [
i32 5, label %if.then
@@ -46,9 +49,11 @@ define void @foo_tail(i1 %i) nounwind {
; CHECK-NEXT: andi $a0, $a0, 1
; CHECK-NEXT: beqz $a0, .LBB1_2
; CHECK-NEXT: # %bb.1: # %if.then
-; CHECK-NEXT: b %plt(bar)
+; CHECK-NEXT: pcaddu18i $t8, %call36(bar)
+; CHECK-NEXT: jr $t8
; CHECK-NEXT: .LBB1_2: # %if.else
-; CHECK-NEXT: b %plt(bar)
+; CHECK-NEXT: pcaddu18i $t8, %call36(bar)
+; CHECK-NEXT: jr $t8
entry:
br i1 %i, label %if.then, label %if.else
diff --git a/llvm/test/CodeGen/LoongArch/numeric-reg-names.ll b/llvm/test/CodeGen/LoongArch/numeric-reg-names.ll
index 10a97a1778df0..5a1158358de13 100644
--- a/llvm/test/CodeGen/LoongArch/numeric-reg-names.ll
+++ b/llvm/test/CodeGen/LoongArch/numeric-reg-names.ll
@@ -31,7 +31,8 @@ define i32 @main() {
; LA64-NEXT: .cfi_offset 1, -8
; LA64-NEXT: pcalau12i $r4, %pc_hi20(.str_1)
; LA64-NEXT: addi.d $r4, $r4, %pc_lo12(.str_1)
-; LA64-NEXT: bl %plt(printf)
+; LA64-NEXT: pcaddu18i $r1, %call36(printf)
+; LA64-NEXT: jirl $r1, $r1, 0
; LA64-NEXT: move $r4, $r0
; LA64-NEXT: ld.d $r1, $r3, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $r3, $r3, 16
diff --git a/llvm/test/CodeGen/LoongArch/sextw-removal.ll b/llvm/test/CodeGen/LoongArch/sextw-removal.ll
index fff749fb13e95..0c31ff9eee1f2 100644
--- a/llvm/test/CodeGen/LoongArch/sextw-removal.ll
+++ b/llvm/test/CodeGen/LoongArch/sextw-removal.ll
@@ -16,7 +16,8 @@ define void @test1(i32 signext %arg, i32 signext %arg1) nounwind {
; CHECK-NEXT: .LBB0_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: move $a0, $s0
-; CHECK-NEXT: bl %plt(bar)
+; CHECK-NEXT: pcaddu18i $ra, %call36(bar)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: sll.w $s0, $s0, $fp
; CHECK-NEXT: bnez $a0, .LBB0_1
; CHECK-NEXT: # %bb.2: # %bb7
@@ -38,7 +39,8 @@ define void @test1(i32 signext %arg, i32 signext %arg1) nounwind {
; NORMV-NEXT: .LBB0_1: # %bb2
; NORMV-NEXT: # =>This Inner Loop Header: Depth=1
; NORMV-NEXT: addi.w $a0, $s0, 0
-; NORMV-NEXT: bl %plt(bar)
+; NORMV-NEXT: pcaddu18i $ra, %call36(bar)
+; NORMV-NEXT: jirl $ra, $ra, 0
; NORMV-NEXT: sll.w $s0, $s0, $fp
; NORMV-NEXT: bnez $a0, .LBB0_1
; NORMV-NEXT: # %bb.2: # %bb7
@@ -149,7 +151,8 @@ define void @test5(i32 signext %arg, i32 signext %arg1) nounwind {
; CHECK-NEXT: .LBB4_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: addi.w $a0, $a1, 0
-; CHECK-NEXT: bl %plt(bar)
+; CHECK-NEXT: pcaddu18i $ra, %call36(bar)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: bstrpick.d $a1, $a0, 31, 0
; CHECK-NEXT: vldi $vr0, 0
; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 0
@@ -170,7 +173,8 @@ define void @test5(i32 signext %arg, i32 signext %arg1) nounwind {
; NORMV-NEXT: .LBB4_1: # %bb2
; NORMV-NEXT: # =>This Inner Loop Header: Depth=1
; NORMV-NEXT: addi.w $a0, $a1, 0
-; NORMV-NEXT: bl %plt(bar)
+; NORMV-NEXT: pcaddu18i $ra, %call36(bar)
+; NORMV-NEXT: jirl $ra, $ra, 0
; NORMV-NEXT: bstrpick.d $a1, $a0, 31, 0
; NORMV-NEXT: vldi $vr0, 0
; NORMV-NEXT: vinsgr2vr.d $vr0, $a1, 0
@@ -209,7 +213,8 @@ define void @test6(i32 signext %arg, i32 signext %arg1) nounwind {
; CHECK-NEXT: .p2align 4, , 16
; CHECK-NEXT: .LBB5_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: bl %plt(baz)
+; CHECK-NEXT: pcaddu18i $ra, %call36(baz)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ftintrz.w.s $fa1, $fa0
; CHECK-NEXT: fcmp.cune.s $fcc0, $fa0, $fs0
; CHECK-NEXT: movfr2gr.s $a0, $fa1
@@ -231,7 +236,8 @@ define void @test6(i32 signext %arg, i32 signext %arg1) nounwind {
; NORMV-NEXT: .LBB5_1: # %bb2
; NORMV-NEXT: # =>This Inner Loop Header: Depth=1
; NORMV-NEXT: addi.w $a0, $a0, 0
-; NORMV-NEXT: bl %plt(baz)
+; NORMV-NEXT: pcaddu18i $ra, %call36(baz)
+; NORMV-NEXT: jirl $ra, $ra, 0
; NORMV-NEXT: ftintrz.w.s $fa1, $fa0
; NORMV-NEXT: fcmp.cune.s $fcc0, $fa0, $fs0
; NORMV-NEXT: movfr2gr.s $a0, $fa1
@@ -267,7 +273,8 @@ define void @test7(i32 signext %arg, i32 signext %arg1) nounwind {
; CHECK-NEXT: .LBB6_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: addi.w $a0, $a0, 0
-; CHECK-NEXT: bl %plt(foo)
+; CHECK-NEXT: pcaddu18i $ra, %call36(foo)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: vldi $vr0, 0
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
; CHECK-NEXT: vpcnt.d $vr0, $vr0
@@ -287,7 +294,8 @@ define void @test7(i32 signext %arg, i32 signext %arg1) nounwind {
; NORMV-NEXT: .LBB6_1: # %bb2
; NORMV-NEXT: # =>This Inner Loop Header: Depth=1
; NORMV-NEXT: addi.w $a0, $a0, 0
-; NORMV-NEXT: bl %plt(foo)
+; NORMV-NEXT: pcaddu18i $ra, %call36(foo)
+; NORMV-NEXT: jirl $ra, $ra, 0
; NORMV-NEXT: vldi $vr0, 0
; NORMV-NEXT: vinsgr2vr.d $vr0, $a0, 0
; NORMV-NEXT: vpcnt.d $vr0, $vr0
@@ -327,7 +335,8 @@ define void @test8(i32 signext %arg, i32 signext %arg1) nounwind {
; CHECK-NEXT: .LBB7_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: addi.w $a0, $a0, 0
-; CHECK-NEXT: bl %plt(foo)
+; CHECK-NEXT: pcaddu18i $ra, %call36(foo)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: or $a0, $a0, $fp
; CHECK-NEXT: bnez $a0, .LBB7_1
; CHECK-NEXT: # %bb.2: # %bb7
@@ -347,7 +356,8 @@ define void @test8(i32 signext %arg, i32 signext %arg1) nounwind {
; NORMV-NEXT: .LBB7_1: # %bb2
; NORMV-NEXT: # =>This Inner Loop Header: Depth=1
; NORMV-NEXT: addi.w $a0, $a0, 0
-; NORMV-NEXT: bl %plt(foo)
+; NORMV-NEXT: pcaddu18i $ra, %call36(foo)
+; NORMV-NEXT: jirl $ra, $ra, 0
; NORMV-NEXT: or $a0, $a0, $fp
; NORMV-NEXT: bnez $a0, .LBB7_1
; NORMV-NEXT: # %bb.2: # %bb7
@@ -384,7 +394,8 @@ define void @test9(i32 signext %arg, i32 signext %arg1) nounwind {
; CHECK-NEXT: .p2align 4, , 16
; CHECK-NEXT: .LBB8_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: bl %plt(bar)
+; CHECK-NEXT: pcaddu18i $ra, %call36(bar)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: move $a1, $a0
; CHECK-NEXT: slti $a0, $a0, 255
; CHECK-NEXT: blt $fp, $a1, .LBB8_1
@@ -405,7 +416,8 @@ define void @test9(i32 signext %arg, i32 signext %arg1) nounwind {
; NORMV-NEXT: .LBB8_1: # %bb2
; NORMV-NEXT: # =>This Inner Loop Header: Depth=1
; NORMV-NEXT: addi.w $a0, $a1, 0
-; NORMV-NEXT: bl %plt(bar)
+; NORMV-NEXT: pcaddu18i $ra, %call36(bar)
+; NORMV-NEXT: jirl $ra, $ra, 0
; NORMV-NEXT: slti $a1, $a0, 255
; NORMV-NEXT: blt $fp, $a0, .LBB8_1
; NORMV-NEXT: # %bb.2: # %bb7
@@ -440,7 +452,8 @@ define void @test10(i32 signext %arg, i32 signext %arg1) nounwind {
; CHECK-NEXT: .p2align 4, , 16
; CHECK-NEXT: .LBB9_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: bl %plt(baz)
+; CHECK-NEXT: pcaddu18i $ra, %call36(baz)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: fcmp.cune.s $fcc0, $fa0, $fs0
; CHECK-NEXT: movfr2gr.s $a0, $fa0
; CHECK-NEXT: bcnez $fcc0, .LBB9_1
@@ -461,7 +474,8 @@ define void @test10(i32 signext %arg, i32 signext %arg1) nounwind {
; NORMV-NEXT: .LBB9_1: # %bb2
; NORMV-NEXT: # =>This Inner Loop Header: Depth=1
; NORMV-NEXT: addi.w $a0, $a0, 0
-; NORMV-NEXT: bl %plt(baz)
+; NORMV-NEXT: pcaddu18i $ra, %call36(baz)
+; NORMV-NEXT: jirl $ra, $ra, 0
; NORMV-NEXT: fcmp.cune.s $fcc0, $fa0, $fs0
; NORMV-NEXT: movfr2gr.s $a0, $fa0
; NORMV-NEXT: bcnez $fcc0, .LBB9_1
@@ -1103,13 +1117,15 @@ define void @test16(i32 signext %arg, i32 signext %arg1) nounwind {
; CHECK-NEXT: st.d $fp, $sp, 16 # 8-byte Folded Spill
; CHECK-NEXT: st.d $s0, $sp, 8 # 8-byte Folded Spill
; CHECK-NEXT: move $fp, $a1
-; CHECK-NEXT: bl %plt(bar)
+; CHECK-NEXT: pcaddu18i $ra, %call36(bar)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: move $s0, $a0
; CHECK-NEXT: .p2align 4, , 16
; CHECK-NEXT: .LBB19_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: move $a0, $s0
-; CHECK-NEXT: bl %plt(bar)
+; CHECK-NEXT: pcaddu18i $ra, %call36(bar)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: sll.w $s0, $s0, $fp
; CHECK-NEXT: bnez $a0, .LBB19_1
; CHECK-NEXT: # %bb.2: # %bb7
@@ -1126,13 +1142,15 @@ define void @test16(i32 signext %arg, i32 signext %arg1) nounwind {
; NORMV-NEXT: st.d $fp, $sp, 16 # 8-byte Folded Spill
; NORMV-NEXT: st.d $s0, $sp, 8 # 8-byte Folded Spill
; NORMV-NEXT: move $fp, $a1
-; NORMV-NEXT: bl %plt(bar)
+; NORMV-NEXT: pcaddu18i $ra, %call36(bar)
+; NORMV-NEXT: jirl $ra, $ra, 0
; NORMV-NEXT: move $s0, $a0
; NORMV-NEXT: .p2align 4, , 16
; NORMV-NEXT: .LBB19_1: # %bb2
; NORMV-NEXT: # =>This Inner Loop Header: Depth=1
; NORMV-NEXT: addi.w $a0, $s0, 0
-; NORMV-NEXT: bl %plt(bar)
+; NORMV-NEXT: pcaddu18i $ra, %call36(bar)
+; NORMV-NEXT: jirl $ra, $ra, 0
; NORMV-NEXT: sll.w $s0, $s0, $fp
; NORMV-NEXT: bnez $a0, .LBB19_1
; NORMV-NEXT: # %bb.2: # %bb7
@@ -1164,13 +1182,15 @@ define void @test17(i32 signext %arg, i32 signext %arg1) nounwind {
; CHECK-NEXT: st.d $fp, $sp, 16 # 8-byte Folded Spill
; CHECK-NEXT: st.d $s0, $sp, 8 # 8-byte Folded Spill
; CHECK-NEXT: move $fp, $a1
-; CHECK-NEXT: bl %plt(bat)
+; CHECK-NEXT: pcaddu18i $ra, %call36(bat)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: move $s0, $a0
; CHECK-NEXT: .p2align 4, , 16
; CHECK-NEXT: .LBB20_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: move $a0, $s0
-; CHECK-NEXT: bl %plt(bar)
+; CHECK-NEXT: pcaddu18i $ra, %call36(bar)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: sll.w $s0, $s0, $fp
; CHECK-NEXT: bnez $a0, .LBB20_1
; CHECK-NEXT: # %bb.2: # %bb7
@@ -1187,13 +1207,15 @@ define void @test17(i32 signext %arg, i32 signext %arg1) nounwind {
; NORMV-NEXT: st.d $fp, $sp, 16 # 8-byte Folded Spill
; NORMV-NEXT: st.d $s0, $sp, 8 # 8-byte Folded Spill
; NORMV-NEXT: move $fp, $a1
-; NORMV-NEXT: bl %plt(bat)
+; NORMV-NEXT: pcaddu18i $ra, %call36(bat)
+; NORMV-NEXT: jirl $ra, $ra, 0
; NORMV-NEXT: move $s0, $a0
; NORMV-NEXT: .p2align 4, , 16
; NORMV-NEXT: .LBB20_1: # %bb2
; NORMV-NEXT: # =>This Inner Loop Header: Depth=1
; NORMV-NEXT: addi.w $a0, $s0, 0
-; NORMV-NEXT: bl %plt(bar)
+; NORMV-NEXT: pcaddu18i $ra, %call36(bar)
+; NORMV-NEXT: jirl $ra, $ra, 0
; NORMV-NEXT: sll.w $s0, $s0, $fp
; NORMV-NEXT: bnez $a0, .LBB20_1
; NORMV-NEXT: # %bb.2: # %bb7
@@ -1266,10 +1288,12 @@ define signext i32 @test19(i64 %arg, i1 zeroext %c1, i1 zeroext %c2, ptr %p) nou
; CHECK-NEXT: beqz $a2, .LBB22_2
; CHECK-NEXT: # %bb.1: # %bb2
; CHECK-NEXT: move $a0, $zero
-; CHECK-NEXT: bl %plt(bar)
+; CHECK-NEXT: pcaddu18i $ra, %call36(bar)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: move $fp, $a0
; CHECK-NEXT: .LBB22_2: # %bb7
-; CHECK-NEXT: bl %plt(side_effect)
+; CHECK-NEXT: pcaddu18i $ra, %call36(side_effect)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: addi.w $a0, $fp, 0
; CHECK-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
@@ -1288,10 +1312,12 @@ define signext i32 @test19(i64 %arg, i1 zeroext %c1, i1 zeroext %c2, ptr %p) nou
; NORMV-NEXT: beqz $a2, .LBB22_2
; NORMV-NEXT: # %bb.1: # %bb2
; NORMV-NEXT: move $a0, $zero
-; NORMV-NEXT: bl %plt(bar)
+; NORMV-NEXT: pcaddu18i $ra, %call36(bar)
+; NORMV-NEXT: jirl $ra, $ra, 0
; NORMV-NEXT: move $fp, $a0
; NORMV-NEXT: .LBB22_2: # %bb7
-; NORMV-NEXT: bl %plt(side_effect)
+; NORMV-NEXT: pcaddu18i $ra, %call36(side_effect)
+; NORMV-NEXT: jirl $ra, $ra, 0
; NORMV-NEXT: addi.w $a0, $fp, 0
; NORMV-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload
; NORMV-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/LoongArch/shrinkwrap.ll b/llvm/test/CodeGen/LoongArch/shrinkwrap.ll
index 8e5ec17d61241..1b1bba90dd7a6 100644
--- a/llvm/test/CodeGen/LoongArch/shrinkwrap.ll
+++ b/llvm/test/CodeGen/LoongArch/shrinkwrap.ll
@@ -14,7 +14,8 @@ define void @eliminate_restore(i32 %n) nounwind {
; NOSHRINKW-NEXT: bltu $a0, $a1, .LBB0_2
; NOSHRINKW-NEXT: b .LBB0_1
; NOSHRINKW-NEXT: .LBB0_1: # %if.then
-; NOSHRINKW-NEXT: bl %plt(abort)
+; NOSHRINKW-NEXT: pcaddu18i $ra, %call36(abort)
+; NOSHRINKW-NEXT: jirl $ra, $ra, 0
; NOSHRINKW-NEXT: .LBB0_2: # %if.end
; NOSHRINKW-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; NOSHRINKW-NEXT: addi.d $sp, $sp, 16
@@ -30,7 +31,8 @@ define void @eliminate_restore(i32 %n) nounwind {
; SHRINKW-NEXT: .LBB0_2: # %if.then
; SHRINKW-NEXT: addi.d $sp, $sp, -16
; SHRINKW-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; SHRINKW-NEXT: bl %plt(abort)
+; SHRINKW-NEXT: pcaddu18i $ra, %call36(abort)
+; SHRINKW-NEXT: jirl $ra, $ra, 0
%cmp = icmp ule i32 %n, 32
br i1 %cmp, label %if.then, label %if.end
@@ -65,7 +67,8 @@ define void @conditional_alloca(i32 %n) nounwind {
; NOSHRINKW-NEXT: move $a0, $sp
; NOSHRINKW-NEXT: sub.d $a0, $a0, $a1
; NOSHRINKW-NEXT: move $sp, $a0
-; NOSHRINKW-NEXT: bl %plt(notdead)
+; NOSHRINKW-NEXT: pcaddu18i $ra, %call36(notdead)
+; NOSHRINKW-NEXT: jirl $ra, $ra, 0
; NOSHRINKW-NEXT: b .LBB1_2
; NOSHRINKW-NEXT: .LBB1_2: # %if.end
; NOSHRINKW-NEXT: addi.d $sp, $fp, -32
@@ -90,7 +93,8 @@ define void @conditional_alloca(i32 %n) nounwind {
; SHRINKW-NEXT: slli.d $a0, $a0, 4
; SHRINKW-NEXT: sub.d $a0, $sp, $a0
; SHRINKW-NEXT: move $sp, $a0
-; SHRINKW-NEXT: bl %plt(notdead)
+; SHRINKW-NEXT: pcaddu18i $ra, %call36(notdead)
+; SHRINKW-NEXT: jirl $ra, $ra, 0
; SHRINKW-NEXT: addi.d $sp, $fp, -16
; SHRINKW-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload
; SHRINKW-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/LoongArch/soft-fp-to-int.ll b/llvm/test/CodeGen/LoongArch/soft-fp-to-int.ll
index ae8c0a6a15ed6..c429d3132f640 100644
--- a/llvm/test/CodeGen/LoongArch/soft-fp-to-int.ll
+++ b/llvm/test/CodeGen/LoongArch/soft-fp-to-int.ll
@@ -25,7 +25,8 @@ define i32 @fptosi_i32_fp128(fp128 %X) nounwind {
; LA64: # %bb.0:
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(__fixtfsi)
+; LA64-NEXT: pcaddu18i $ra, %call36(__fixtfsi)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
@@ -47,7 +48,8 @@ define i32 @fptosi_i32_double(double %X) nounwind {
; LA64: # %bb.0:
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(__fixdfsi)
+; LA64-NEXT: pcaddu18i $ra, %call36(__fixdfsi)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
@@ -69,7 +71,8 @@ define i32 @fptosi_i32_float(float %X) nounwind {
; LA64: # %bb.0:
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(__fixsfsi)
+; LA64-NEXT: pcaddu18i $ra, %call36(__fixsfsi)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
@@ -100,7 +103,8 @@ define i64 @fptosi_i64_fp128(fp128 %X) nounwind {
; LA64: # %bb.0:
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(__fixtfdi)
+; LA64-NEXT: pcaddu18i $ra, %call36(__fixtfdi)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
@@ -122,7 +126,8 @@ define i64 @fptosi_i64_double(double %X) nounwind {
; LA64: # %bb.0:
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(__fixdfdi)
+; LA64-NEXT: pcaddu18i $ra, %call36(__fixdfdi)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
@@ -144,7 +149,8 @@ define i64 @fptosi_i64_float(float %X) nounwind {
; LA64: # %bb.0:
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; LA64-NEXT: bl %plt(__fixsfdi)
+; LA64-NEXT: pcaddu18i $ra, %call36(__fixsfdi)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/spill-reload-cfr.ll b/llvm/test/CodeGen/LoongArch/spill-reload-cfr.ll
index 8dd95befb8278..9cb364e05c326 100644
--- a/llvm/test/CodeGen/LoongArch/spill-reload-cfr.ll
+++ b/llvm/test/CodeGen/LoongArch/spill-reload-cfr.ll
@@ -47,7 +47,8 @@ define i1 @load_store_fcc_reg(float %a, i1 %c) {
; LA64-NEXT: .cfi_offset 56, -24
; LA64-NEXT: move $fp, $a0
; LA64-NEXT: fmov.s $fs0, $fa0
-; LA64-NEXT: bl %plt(foo)
+; LA64-NEXT: pcaddu18i $ra, %call36(foo)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: movgr2fr.w $fa0, $zero
; LA64-NEXT: fcmp.cult.s $fcc0, $fa0, $fs0
; LA64-NEXT: bcnez $fcc0, .LBB0_2
diff --git a/llvm/test/CodeGen/LoongArch/split-sp-adjust.ll b/llvm/test/CodeGen/LoongArch/split-sp-adjust.ll
index 0605ceedf3e2b..8578ec2523add 100644
--- a/llvm/test/CodeGen/LoongArch/split-sp-adjust.ll
+++ b/llvm/test/CodeGen/LoongArch/split-sp-adjust.ll
@@ -10,7 +10,8 @@ define i32 @SplitSP() nounwind {
; CHECK-NEXT: st.d $ra, $sp, 2024 # 8-byte Folded Spill
; CHECK-NEXT: addi.d $sp, $sp, -16
; CHECK-NEXT: addi.d $a0, $sp, 12
-; CHECK-NEXT: bl %plt(foo)
+; CHECK-NEXT: pcaddu18i $ra, %call36(foo)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: move $a0, $zero
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ld.d $ra, $sp, 2024 # 8-byte Folded Reload
@@ -31,7 +32,8 @@ define i32 @NoSplitSP() nounwind {
; CHECK-NEXT: addi.d $sp, $sp, -2032
; CHECK-NEXT: st.d $ra, $sp, 2024 # 8-byte Folded Spill
; CHECK-NEXT: addi.d $a0, $sp, 8
-; CHECK-NEXT: bl %plt(foo)
+; CHECK-NEXT: pcaddu18i $ra, %call36(foo)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: move $a0, $zero
; CHECK-NEXT: ld.d $ra, $sp, 2024 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 2032
diff --git a/llvm/test/CodeGen/LoongArch/stack-realignment-with-variable-sized-objects.ll b/llvm/test/CodeGen/LoongArch/stack-realignment-with-variable-sized-objects.ll
index 1246b8bfa1105..f6c6c5aa225c6 100644
--- a/llvm/test/CodeGen/LoongArch/stack-realignment-with-variable-sized-objects.ll
+++ b/llvm/test/CodeGen/LoongArch/stack-realignment-with-variable-sized-objects.ll
@@ -55,7 +55,8 @@ define void @caller(i32 %n) {
; LA64-NEXT: sub.d $a0, $sp, $a0
; LA64-NEXT: move $sp, $a0
; LA64-NEXT: addi.d $a1, $s8, 0
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: addi.d $sp, $fp, -64
; LA64-NEXT: ld.d $s8, $sp, 40 # 8-byte Folded Reload
; LA64-NEXT: ld.d $fp, $sp, 48 # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/LoongArch/stack-realignment.ll b/llvm/test/CodeGen/LoongArch/stack-realignment.ll
index 43e61adb2bdc9..6d4210eb5b647 100644
--- a/llvm/test/CodeGen/LoongArch/stack-realignment.ll
+++ b/llvm/test/CodeGen/LoongArch/stack-realignment.ll
@@ -38,7 +38,8 @@ define void @caller32() {
; LA64-NEXT: .cfi_def_cfa 22, 0
; LA64-NEXT: bstrins.d $sp, $zero, 4, 0
; LA64-NEXT: addi.d $a0, $sp, 0
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: addi.d $sp, $fp, -32
; LA64-NEXT: ld.d $fp, $sp, 16 # 8-byte Folded Reload
; LA64-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload
@@ -69,7 +70,8 @@ define void @caller_no_realign32() "no-realign-stack" {
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: .cfi_offset 1, -8
; LA64-NEXT: addi.d $a0, $sp, 0
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
@@ -110,7 +112,8 @@ define void @caller64() {
; LA64-NEXT: .cfi_def_cfa 22, 0
; LA64-NEXT: bstrins.d $sp, $zero, 5, 0
; LA64-NEXT: addi.d $a0, $sp, 0
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: addi.d $sp, $fp, -64
; LA64-NEXT: ld.d $fp, $sp, 48 # 8-byte Folded Reload
; LA64-NEXT: ld.d $ra, $sp, 56 # 8-byte Folded Reload
@@ -141,7 +144,8 @@ define void @caller_no_realign64() "no-realign-stack" {
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: .cfi_offset 1, -8
; LA64-NEXT: addi.d $a0, $sp, 0
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
@@ -182,7 +186,8 @@ define void @caller128() {
; LA64-NEXT: .cfi_def_cfa 22, 0
; LA64-NEXT: bstrins.d $sp, $zero, 6, 0
; LA64-NEXT: addi.d $a0, $sp, 0
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: addi.d $sp, $fp, -128
; LA64-NEXT: ld.d $fp, $sp, 112 # 8-byte Folded Reload
; LA64-NEXT: ld.d $ra, $sp, 120 # 8-byte Folded Reload
@@ -213,7 +218,8 @@ define void @caller_no_realign128() "no-realign-stack" {
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: .cfi_offset 1, -8
; LA64-NEXT: addi.d $a0, $sp, 0
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
@@ -254,7 +260,8 @@ define void @caller256() {
; LA64-NEXT: .cfi_def_cfa 22, 0
; LA64-NEXT: bstrins.d $sp, $zero, 7, 0
; LA64-NEXT: addi.d $a0, $sp, 0
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: addi.d $sp, $fp, -256
; LA64-NEXT: ld.d $fp, $sp, 240 # 8-byte Folded Reload
; LA64-NEXT: ld.d $ra, $sp, 248 # 8-byte Folded Reload
@@ -285,7 +292,8 @@ define void @caller_no_realign256() "no-realign-stack" {
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: .cfi_offset 1, -8
; LA64-NEXT: addi.d $a0, $sp, 0
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
@@ -326,7 +334,8 @@ define void @caller512() {
; LA64-NEXT: .cfi_def_cfa 22, 0
; LA64-NEXT: bstrins.d $sp, $zero, 8, 0
; LA64-NEXT: addi.d $a0, $sp, 512
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: addi.d $sp, $fp, -1024
; LA64-NEXT: ld.d $fp, $sp, 1008 # 8-byte Folded Reload
; LA64-NEXT: ld.d $ra, $sp, 1016 # 8-byte Folded Reload
@@ -357,7 +366,8 @@ define void @caller_no_realign512() "no-realign-stack" {
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: .cfi_offset 1, -8
; LA64-NEXT: addi.d $a0, $sp, 0
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
@@ -401,7 +411,8 @@ define void @caller1024() {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: bstrins.d $sp, $zero, 9, 0
; LA64-NEXT: addi.d $a0, $sp, 1024
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: addi.d $sp, $fp, -2048
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ld.d $fp, $sp, 2016 # 8-byte Folded Reload
@@ -433,7 +444,8 @@ define void @caller_no_realign1024() "no-realign-stack" {
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: .cfi_offset 1, -8
; LA64-NEXT: addi.d $a0, $sp, 0
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
@@ -483,7 +495,8 @@ define void @caller2048() {
; LA64-NEXT: bstrins.d $sp, $zero, 10, 0
; LA64-NEXT: ori $a0, $zero, 2048
; LA64-NEXT: add.d $a0, $sp, $a0
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: lu12i.w $a0, 1
; LA64-NEXT: sub.d $sp, $fp, $a0
; LA64-NEXT: addi.d $sp, $sp, 2032
@@ -517,7 +530,8 @@ define void @caller_no_realign2048() "no-realign-stack" {
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: .cfi_offset 1, -8
; LA64-NEXT: addi.d $a0, $sp, 0
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
@@ -570,7 +584,8 @@ define void @caller4096() {
; LA64-NEXT: bstrins.d $sp, $zero, 11, 0
; LA64-NEXT: lu12i.w $a0, 1
; LA64-NEXT: add.d $a0, $sp, $a0
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: lu12i.w $a0, 2
; LA64-NEXT: sub.d $sp, $fp, $a0
; LA64-NEXT: lu12i.w $a0, 1
@@ -605,7 +620,8 @@ define void @caller_no_realign4096() "no-realign-stack" {
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: .cfi_offset 1, -8
; LA64-NEXT: addi.d $a0, $sp, 0
-; LA64-NEXT: bl %plt(callee)
+; LA64-NEXT: pcaddu18i $ra, %call36(callee)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/statepoint-call-lowering.ll b/llvm/test/CodeGen/LoongArch/statepoint-call-lowering.ll
index 40e98582b3bc9..1926dbd423153 100644
--- a/llvm/test/CodeGen/LoongArch/statepoint-call-lowering.ll
+++ b/llvm/test/CodeGen/LoongArch/statepoint-call-lowering.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch64 -verify-machineinstrs < %s | FileCheck %s
;; A collection of basic functionality tests for statepoint lowering - most
;; interesting cornercases are exercised through the x86 tests.
@@ -164,7 +165,8 @@ define i1 @test_cross_bb(ptr addrspace(1) %a, i1 %external_cond) nounwind gc "st
; CHECK-NEXT: ld.d $a1, $sp, 8
; CHECK-NEXT: move $fp, $a0
; CHECK-NEXT: move $a0, $a1
-; CHECK-NEXT: bl %plt(consume)
+; CHECK-NEXT: pcaddu18i $ra, %call36(consume)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: move $a0, $fp
; CHECK-NEXT: b .LBB8_3
; CHECK-NEXT: .LBB8_2: # %right
diff --git a/llvm/test/CodeGen/LoongArch/tail-calls.ll b/llvm/test/CodeGen/LoongArch/tail-calls.ll
index 7f315ee897b1c..533761c8a1c70 100644
--- a/llvm/test/CodeGen/LoongArch/tail-calls.ll
+++ b/llvm/test/CodeGen/LoongArch/tail-calls.ll
@@ -6,7 +6,8 @@ declare i32 @callee_tail(i32 %i)
define i32 @caller_tail(i32 %i) nounwind {
; CHECK-LABEL: caller_tail:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: b %plt(callee_tail)
+; CHECK-NEXT: pcaddu18i $t8, %call36(callee_tail)
+; CHECK-NEXT: jr $t8
entry:
%r = tail call i32 @callee_tail(i32 %i)
ret i32 %r
@@ -25,7 +26,8 @@ define void @caller_extern(ptr %src) optsize {
; CHECK-NEXT: move $a3, $a0
; CHECK-NEXT: move $a0, $a1
; CHECK-NEXT: move $a1, $a3
-; CHECK-NEXT: b %plt(memcpy)
+; CHECK-NEXT: pcaddu18i $t8, %call36(memcpy)
+; CHECK-NEXT: jr $t8
entry:
tail call void @llvm.memcpy.p0.p0.i32(ptr @dest, ptr %src, i32 33, i1 false)
ret void
@@ -68,7 +70,8 @@ define void @caller_varargs(i32 %a, i32 %b) nounwind {
; CHECK-NEXT: move $a5, $a1
; CHECK-NEXT: move $a6, $a1
; CHECK-NEXT: move $a7, $a0
-; CHECK-NEXT: bl %plt(callee_varargs)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_varargs)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
@@ -86,7 +89,8 @@ define i32 @caller_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %g
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; CHECK-NEXT: ld.d $t0, $sp, 16
; CHECK-NEXT: st.d $t0, $sp, 0
-; CHECK-NEXT: bl %plt(callee_args)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_args)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
@@ -108,7 +112,8 @@ define void @caller_indirect_args() nounwind {
; CHECK-NEXT: ori $a1, $zero, 1
; CHECK-NEXT: addi.d $a0, $sp, 0
; CHECK-NEXT: st.d $a1, $sp, 0
-; CHECK-NEXT: bl %plt(callee_indirect_args)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_indirect_args)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 40 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 48
; CHECK-NEXT: ret
@@ -127,7 +132,8 @@ define i32 @caller_byval() nounwind {
; CHECK-NEXT: ld.d $a0, $sp, 16
; CHECK-NEXT: st.d $a0, $sp, 8
; CHECK-NEXT: addi.d $a0, $sp, 8
-; CHECK-NEXT: bl %plt(callee_byval)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_byval)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 32
; CHECK-NEXT: ret
@@ -149,7 +155,8 @@ define void @caller_nostruct() nounwind {
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; CHECK-NEXT: pcalau12i $a0, %got_pc_hi20(a)
; CHECK-NEXT: ld.d $a0, $a0, %got_pc_lo12(a)
-; CHECK-NEXT: bl %plt(callee_struct)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_struct)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
@@ -165,7 +172,8 @@ define void @caller_struct(ptr sret(%struct.A) %a) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi.d $sp, $sp, -16
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT: bl %plt(callee_nostruct)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_nostruct)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
@@ -180,7 +188,8 @@ define i32 @disable_tail_calls(i32 %i) nounwind "disable-tail-calls"="true" {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi.d $sp, $sp, -16
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT: bl %plt(callee_tail)
+; CHECK-NEXT: pcaddu18i $ra, %call36(callee_tail)
+; CHECK-NEXT: jirl $ra, $ra, 0
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/target-abi-from-triple-edge-cases.ll b/llvm/test/CodeGen/LoongArch/target-abi-from-triple-edge-cases.ll
index 147b792361478..eb656ad94e28b 100644
--- a/llvm/test/CodeGen/LoongArch/target-abi-from-triple-edge-cases.ll
+++ b/llvm/test/CodeGen/LoongArch/target-abi-from-triple-edge-cases.ll
@@ -71,7 +71,8 @@ define float @f(float %a) {
; LP64D-NEXT: ret
;
; LP64S-LP64F-NOF-LABEL: f:
-; LP64S-LP64F-NOF: bl %plt(__addsf3)
+; LP64S-LP64F-NOF: pcaddu18i $ra, %call36(__addsf3)
+; LP64S-LP64F-NOF-NEXT: jirl $ra, $ra, 0
;
; LP64S-LP64D-NOD-LABEL: f:
; LP64S-LP64D-NOD: # %bb.0:
@@ -84,10 +85,12 @@ define float @f(float %a) {
; LP64S-LP64D-NOD-NEXT: ret
;
; LP64D-LP64F-NOF-LABEL: f:
-; LP64D-LP64F-NOF: bl %plt(__addsf3)
+; LP64D-LP64F-NOF: pcaddu18i $ra, %call36(__addsf3)
+; LP64D-LP64F-NOF-NEXT: jirl $ra, $ra, 0
;
; LP64D-NONE-NOF-LABEL: f:
-; LP64D-NONE-NOF: bl %plt(__addsf3)
+; LP64D-NONE-NOF: pcaddu18i $ra, %call36(__addsf3)
+; LP64D-NONE-NOF-NEXT: jirl $ra, $ra, 0
%1 = fadd float %a, 1.0
ret float %1
}
@@ -109,7 +112,8 @@ define double @g(double %a) {
; LP64D-NEXT: ret
;
; LP64S-LABEL: g:
-; LP64S: bl %plt(__adddf3)
+; LP64S: pcaddu18i $ra, %call36(__adddf3)
+; LP64S-NEXT: jirl $ra, $ra, 0
%1 = fadd double %a, 1.0
ret double %1
}
diff --git a/llvm/test/CodeGen/LoongArch/tls-models.ll b/llvm/test/CodeGen/LoongArch/tls-models.ll
index e3a8ace3bc7e3..ffd480a4bd840 100644
--- a/llvm/test/CodeGen/LoongArch/tls-models.ll
+++ b/llvm/test/CodeGen/LoongArch/tls-models.ll
@@ -41,7 +41,8 @@ define ptr @f1() nounwind {
; LA64PIC-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64PIC-NEXT: pcalau12i $a0, %gd_pc_hi20(unspecified)
; LA64PIC-NEXT: addi.d $a0, $a0, %got_pc_lo12(unspecified)
-; LA64PIC-NEXT: bl %plt(__tls_get_addr)
+; LA64PIC-NEXT: pcaddu18i $ra, %call36(__tls_get_addr)
+; LA64PIC-NEXT: jirl $ra, $ra, 0
; LA64PIC-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64PIC-NEXT: addi.d $sp, $sp, 16
; LA64PIC-NEXT: ret
@@ -154,7 +155,8 @@ define ptr @f2() nounwind {
; LA64PIC-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64PIC-NEXT: pcalau12i $a0, %ld_pc_hi20(ld)
; LA64PIC-NEXT: addi.d $a0, $a0, %got_pc_lo12(ld)
-; LA64PIC-NEXT: bl %plt(__tls_get_addr)
+; LA64PIC-NEXT: pcaddu18i $ra, %call36(__tls_get_addr)
+; LA64PIC-NEXT: jirl $ra, $ra, 0
; LA64PIC-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64PIC-NEXT: addi.d $sp, $sp, 16
; LA64PIC-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/unaligned-memcpy-inline.ll b/llvm/test/CodeGen/LoongArch/unaligned-memcpy-inline.ll
index ad48778d2d0ba..5ab20b83b5f82 100644
--- a/llvm/test/CodeGen/LoongArch/unaligned-memcpy-inline.ll
+++ b/llvm/test/CodeGen/LoongArch/unaligned-memcpy-inline.ll
@@ -27,7 +27,8 @@ define void @t0(ptr %out, ptr %in) {
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: .cfi_offset 1, -8
; LA64-NEXT: ori $a2, $zero, 16
-; LA64-NEXT: bl %plt(memcpy)
+; LA64-NEXT: pcaddu18i $ra, %call36(memcpy)
+; LA64-NEXT: jirl $ra, $ra, 0
; LA64-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/vararg.ll b/llvm/test/CodeGen/LoongArch/vararg.ll
index f488610868eb3..939cd2015c5b1 100644
--- a/llvm/test/CodeGen/LoongArch/vararg.ll
+++ b/llvm/test/CodeGen/LoongArch/vararg.ll
@@ -131,7 +131,8 @@ define i64 @va1_va_arg_alloca(ptr %fmt, ...) nounwind {
; LA64-FPELIM-NEXT: bstrins.d $a0, $zero, 3, 0
; LA64-FPELIM-NEXT: sub.d $a0, $sp, $a0
; LA64-FPELIM-NEXT: move $sp, $a0
-; LA64-FPELIM-NEXT: bl %plt(notdead)
+; LA64-FPELIM-NEXT: pcaddu18i $ra, %call36(notdead)
+; LA64-FPELIM-NEXT: jirl $ra, $ra, 0
; LA64-FPELIM-NEXT: move $a0, $s0
; LA64-FPELIM-NEXT: addi.d $sp, $fp, -32
; LA64-FPELIM-NEXT: ld.d $s0, $sp, 8 # 8-byte Folded Reload
@@ -161,7 +162,8 @@ define i64 @va1_va_arg_alloca(ptr %fmt, ...) nounwind {
; LA64-WITHFP-NEXT: bstrins.d $a0, $zero, 3, 0
; LA64-WITHFP-NEXT: sub.d $a0, $sp, $a0
; LA64-WITHFP-NEXT: move $sp, $a0
-; LA64-WITHFP-NEXT: bl %plt(notdead)
+; LA64-WITHFP-NEXT: pcaddu18i $ra, %call36(notdead)
+; LA64-WITHFP-NEXT: jirl $ra, $ra, 0
; LA64-WITHFP-NEXT: move $a0, $s0
; LA64-WITHFP-NEXT: addi.d $sp, $fp, -32
; LA64-WITHFP-NEXT: ld.d $s0, $sp, 8 # 8-byte Folded Reload
@@ -185,7 +187,8 @@ define void @va1_caller() nounwind {
; LA64-FPELIM-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-FPELIM-NEXT: lu52i.d $a1, $zero, 1023
; LA64-FPELIM-NEXT: ori $a2, $zero, 2
-; LA64-FPELIM-NEXT: bl %plt(va1)
+; LA64-FPELIM-NEXT: pcaddu18i $ra, %call36(va1)
+; LA64-FPELIM-NEXT: jirl $ra, $ra, 0
; LA64-FPELIM-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-FPELIM-NEXT: addi.d $sp, $sp, 16
; LA64-FPELIM-NEXT: ret
@@ -198,7 +201,8 @@ define void @va1_caller() nounwind {
; LA64-WITHFP-NEXT: addi.d $fp, $sp, 16
; LA64-WITHFP-NEXT: lu52i.d $a1, $zero, 1023
; LA64-WITHFP-NEXT: ori $a2, $zero, 2
-; LA64-WITHFP-NEXT: bl %plt(va1)
+; LA64-WITHFP-NEXT: pcaddu18i $ra, %call36(va1)
+; LA64-WITHFP-NEXT: jirl $ra, $ra, 0
; LA64-WITHFP-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload
; LA64-WITHFP-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-WITHFP-NEXT: addi.d $sp, $sp, 16
@@ -228,7 +232,8 @@ define void @va_aligned_register_caller() nounwind {
; LA64-FPELIM-NEXT: ori $a0, $zero, 2
; LA64-FPELIM-NEXT: ori $a1, $zero, 1111
; LA64-FPELIM-NEXT: move $a2, $zero
-; LA64-FPELIM-NEXT: bl %plt(va_aligned_register)
+; LA64-FPELIM-NEXT: pcaddu18i $ra, %call36(va_aligned_register)
+; LA64-FPELIM-NEXT: jirl $ra, $ra, 0
; LA64-FPELIM-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-FPELIM-NEXT: addi.d $sp, $sp, 16
; LA64-FPELIM-NEXT: ret
@@ -250,7 +255,8 @@ define void @va_aligned_register_caller() nounwind {
; LA64-WITHFP-NEXT: ori $a0, $zero, 2
; LA64-WITHFP-NEXT: ori $a1, $zero, 1111
; LA64-WITHFP-NEXT: move $a2, $zero
-; LA64-WITHFP-NEXT: bl %plt(va_aligned_register)
+; LA64-WITHFP-NEXT: pcaddu18i $ra, %call36(va_aligned_register)
+; LA64-WITHFP-NEXT: jirl $ra, $ra, 0
; LA64-WITHFP-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload
; LA64-WITHFP-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; LA64-WITHFP-NEXT: addi.d $sp, $sp, 16
@@ -300,7 +306,8 @@ define void @va_aligned_stack_caller() nounwind {
; LA64-FPELIM-NEXT: ori $a7, $zero, 1
; LA64-FPELIM-NEXT: st.d $a5, $sp, 64
; LA64-FPELIM-NEXT: move $a6, $zero
-; LA64-FPELIM-NEXT: bl %plt(va_aligned_stack_callee)
+; LA64-FPELIM-NEXT: pcaddu18i $ra, %call36(va_aligned_stack_callee)
+; LA64-FPELIM-NEXT: jirl $ra, $ra, 0
; LA64-FPELIM-NEXT: ld.d $ra, $sp, 104 # 8-byte Folded Reload
; LA64-FPELIM-NEXT: addi.d $sp, $sp, 112
; LA64-FPELIM-NEXT: ret
@@ -341,7 +348,8 @@ define void @va_aligned_stack_caller() nounwind {
; LA64-WITHFP-NEXT: ori $a7, $zero, 1
; LA64-WITHFP-NEXT: st.d $a5, $fp, -48
; LA64-WITHFP-NEXT: move $a6, $zero
-; LA64-WITHFP-NEXT: bl %plt(va_aligned_stack_callee)
+; LA64-WITHFP-NEXT: pcaddu18i $ra, %call36(va_aligned_stack_callee)
+; LA64-WITHFP-NEXT: jirl $ra, $ra, 0
; LA64-WITHFP-NEXT: ld.d $fp, $sp, 96 # 8-byte Folded Reload
; LA64-WITHFP-NEXT: ld.d $ra, $sp, 104 # 8-byte Folded Reload
; LA64-WITHFP-NEXT: addi.d $sp, $sp, 112
diff --git a/llvm/test/CodeGen/LoongArch/vector-fp-imm.ll b/llvm/test/CodeGen/LoongArch/vector-fp-imm.ll
index 0bdace6b60112..d043eefb96a50 100644
--- a/llvm/test/CodeGen/LoongArch/vector-fp-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/vector-fp-imm.ll
@@ -427,11 +427,13 @@ define void @test_d2(ptr %P, ptr %S) nounwind {
; LA64F-NEXT: ld.d $a0, $a0, 0
; LA64F-NEXT: move $s0, $a1
; LA64F-NEXT: lu52i.d $a1, $zero, 1023
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: move $s1, $a0
; LA64F-NEXT: lu52i.d $a1, $zero, 1024
; LA64F-NEXT: move $a0, $fp
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $a0, $s0, 8
; LA64F-NEXT: st.d $s1, $s0, 0
; LA64F-NEXT: ld.d $s1, $sp, 0 # 8-byte Folded Reload
@@ -568,19 +570,23 @@ define void @test_d4(ptr %P, ptr %S) nounwind {
; LA64F-NEXT: ori $a1, $zero, 0
; LA64F-NEXT: lu32i.d $a1, -524288
; LA64F-NEXT: lu52i.d $a1, $a1, 1024
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: move $s3, $a0
; LA64F-NEXT: lu52i.d $a1, $zero, 1023
; LA64F-NEXT: move $a0, $s1
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: move $s1, $a0
; LA64F-NEXT: lu52i.d $a1, $zero, 1024
; LA64F-NEXT: move $a0, $s0
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: move $s0, $a0
; LA64F-NEXT: lu52i.d $a1, $zero, 1025
; LA64F-NEXT: move $a0, $fp
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $a0, $s2, 24
; LA64F-NEXT: st.d $s0, $s2, 8
; LA64F-NEXT: st.d $s1, $s2, 0
@@ -807,38 +813,46 @@ define void @test_d8(ptr %P, ptr %S) nounwind {
; LA64F-NEXT: lu32i.d $a1, -524288
; LA64F-NEXT: lu52i.d $s7, $a1, 1024
; LA64F-NEXT: move $a1, $s7
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $a0, $sp, 8 # 8-byte Folded Spill
; LA64F-NEXT: move $a0, $s6
; LA64F-NEXT: move $a1, $s7
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: move $s6, $a0
; LA64F-NEXT: lu52i.d $s7, $zero, 1023
; LA64F-NEXT: move $a0, $s5
; LA64F-NEXT: move $a1, $s7
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: move $s5, $a0
; LA64F-NEXT: lu52i.d $s0, $zero, 1024
; LA64F-NEXT: move $a0, $s4
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: move $s4, $a0
; LA64F-NEXT: lu52i.d $s8, $zero, 1025
; LA64F-NEXT: move $a0, $s3
; LA64F-NEXT: move $a1, $s8
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: move $s3, $a0
; LA64F-NEXT: move $a0, $s2
; LA64F-NEXT: move $a1, $s7
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: move $s2, $a0
; LA64F-NEXT: move $a0, $s1
; LA64F-NEXT: move $a1, $s0
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: move $s0, $a0
; LA64F-NEXT: ld.d $a0, $sp, 16 # 8-byte Folded Reload
; LA64F-NEXT: move $a1, $s8
-; LA64F-NEXT: bl %plt(__adddf3)
+; LA64F-NEXT: pcaddu18i $ra, %call36(__adddf3)
+; LA64F-NEXT: jirl $ra, $ra, 0
; LA64F-NEXT: st.d $a0, $fp, 56
; LA64F-NEXT: st.d $s0, $fp, 40
; LA64F-NEXT: st.d $s2, $fp, 32
>From 934abb792629a5d3725e09770c45d1586f0cb726 Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui at loongson.cn>
Date: Thu, 20 Mar 2025 19:56:22 +0800
Subject: [PATCH 2/2] [docs] Add the code model changes to the release notes
---
llvm/docs/ReleaseNotes.md | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 205c2ad25f23e..e5b7f1f656f59 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -105,6 +105,8 @@ Changes to the Hexagon Backend
Changes to the LoongArch Backend
--------------------------------
+* Changing the default code model from `small` to `medium` for 64-bit.
+
Changes to the MIPS Backend
---------------------------
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