[llvm] [PowerPC] dmr extract update assembly operand order (PR #132083)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 19 11:59:29 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-powerpc
Author: None (RolandF77)
<details>
<summary>Changes</summary>
The operand order of the assembly for dmr extract instructions has changed since they were added. The results now come before the uses.
---
Patch is 46.71 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/132083.diff
9 Files Affected:
- (modified) llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td (+3-3)
- (modified) llvm/test/CodeGen/PowerPC/dmf-outer-product.ll (+24-24)
- (modified) llvm/test/CodeGen/PowerPC/dmr-enable.ll (+12-12)
- (modified) llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll (+4-4)
- (modified) llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll (+60-60)
- (modified) llvm/test/CodeGen/PowerPC/v1024ls.ll (+4-4)
- (modified) llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt (+4-4)
- (modified) llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt (+4-4)
- (modified) llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s (+12-12)
``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
index f7f2c855da5d7..d4f0e222b457c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
@@ -163,14 +163,14 @@ let Predicates = [IsISAFuture] in {
def DMXXEXTFDMR512 : XX3Form_AT3_XABp5_P1<60, 226,
(outs vsrprc:$XAp, vsrprc:$XBp),
(ins wacc:$AT),
- "dmxxextfdmr512 $AT, $XAp, $XBp, 0", []> {
+ "dmxxextfdmr512 $XAp, $XBp, $AT, 0", []> {
let P = 0;
}
def DMXXEXTFDMR512_HI : XX3Form_AT3_XABp5_P1<60, 226,
(outs vsrprc:$XAp, vsrprc:$XBp),
(ins wacc_hi:$AT),
- "dmxxextfdmr512 $AT, $XAp, $XBp, 1", []> {
+ "dmxxextfdmr512 $XAp, $XBp, $AT, 1", []> {
let P = 1;
}
@@ -188,7 +188,7 @@ let Predicates = [IsISAFuture] in {
def DMXXEXTFDMR256 : XX2Form_AT3_XBp5_P2<60, 484, (outs vsrprc:$XBp),
(ins dmrrowp:$AT, u2imm:$P),
- "dmxxextfdmr256 $AT, $XBp, $P", []>;
+ "dmxxextfdmr256 $XBp, $AT, $P", []>;
def DMXXINSTFDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
(ins vsrprc:$XBp, u2imm:$P),
diff --git a/llvm/test/CodeGen/PowerPC/dmf-outer-product.ll b/llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
index e00e5c1ba0d6c..cba52567c900d 100644
--- a/llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
+++ b/llvm/test/CodeGen/PowerPC/dmf-outer-product.ll
@@ -15,10 +15,10 @@ define void @test_dmxvi8gerx4(ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-NEXT: lxv vs0, 0(r4)
; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: dmxvi8gerx4 dmr0, vsp34, vs0
-; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r5)
; CHECK-NEXT: stxvp vsp36, 64(r5)
-; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r5)
; CHECK-NEXT: stxvp vsp36, 0(r5)
; CHECK-NEXT: blr
@@ -29,10 +29,10 @@ define void @test_dmxvi8gerx4(ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: lxv v3, 16(r3)
; CHECK-BE-NEXT: dmxvi8gerx4 dmr0, vsp34, vs0
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
; CHECK-BE-NEXT: blr
@@ -59,10 +59,10 @@ define void @test_dmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-NEXT: lxv vs0, 0(r5)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: dmxvi8gerx4pp dmr0, vsp34, vs0
-; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r6)
; CHECK-NEXT: stxvp vsp36, 64(r6)
-; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r6)
; CHECK-NEXT: stxvp vsp36, 0(r6)
; CHECK-NEXT: blr
@@ -79,10 +79,10 @@ define void @test_dmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE-NEXT: lxv vs0, 0(r5)
; CHECK-BE-NEXT: lxv v3, 16(r4)
; CHECK-BE-NEXT: dmxvi8gerx4pp dmr0, vsp34, vs0
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r6)
; CHECK-BE-NEXT: stxvp vsp34, 0(r6)
; CHECK-BE-NEXT: blr
@@ -110,10 +110,10 @@ define void @test_dmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-NEXT: lxv vs0, 0(r5)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: dmxvi8gerx4spp dmr0, vsp34, vs0
-; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r6)
; CHECK-NEXT: stxvp vsp36, 64(r6)
-; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r6)
; CHECK-NEXT: stxvp vsp36, 0(r6)
; CHECK-NEXT: blr
@@ -130,10 +130,10 @@ define void @test_dmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE-NEXT: lxv vs0, 0(r5)
; CHECK-BE-NEXT: lxv v3, 16(r4)
; CHECK-BE-NEXT: dmxvi8gerx4spp dmr0, vsp34, vs0
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r6)
; CHECK-BE-NEXT: stxvp vsp34, 0(r6)
; CHECK-BE-NEXT: blr
@@ -161,10 +161,10 @@ define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-NEXT: lxv vs0, 0(r5)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: pmdmxvi8gerx4pp dmr0, vsp34, vs0, 42, 7, 9
-; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r6)
; CHECK-NEXT: stxvp vsp36, 64(r6)
-; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r6)
; CHECK-NEXT: stxvp vsp36, 0(r6)
; CHECK-NEXT: blr
@@ -181,10 +181,10 @@ define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE-NEXT: lxv vs0, 0(r5)
; CHECK-BE-NEXT: lxv v3, 16(r4)
; CHECK-BE-NEXT: pmdmxvi8gerx4pp dmr0, vsp34, vs0, 42, 7, 9
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r6)
; CHECK-BE-NEXT: stxvp vsp34, 0(r6)
; CHECK-BE-NEXT: blr
@@ -206,10 +206,10 @@ define void @test_pmdmxvi8gerx4(ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-NEXT: lxv vs0, 0(r4)
; CHECK-NEXT: lxv v3, 0(r3)
; CHECK-NEXT: pmdmxvi8gerx4 dmr0, vsp34, vs0, 55, 5, 10
-; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r5)
; CHECK-NEXT: stxvp vsp36, 64(r5)
-; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r5)
; CHECK-NEXT: stxvp vsp36, 0(r5)
; CHECK-NEXT: blr
@@ -220,10 +220,10 @@ define void @test_pmdmxvi8gerx4(ptr %vpp, ptr %vcp, ptr %resp) {
; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: lxv v3, 16(r3)
; CHECK-BE-NEXT: pmdmxvi8gerx4 dmr0, vsp34, vs0, 55, 5, 10
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
; CHECK-BE-NEXT: blr
@@ -250,10 +250,10 @@ define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %
; CHECK-NEXT: lxv vs0, 0(r5)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: pmdmxvi8gerx4spp dmr0, vsp34, vs0, 100, 6, 12
-; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r6)
; CHECK-NEXT: stxvp vsp36, 64(r6)
-; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r6)
; CHECK-NEXT: stxvp vsp36, 0(r6)
; CHECK-NEXT: blr
@@ -270,10 +270,10 @@ define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %
; CHECK-BE-NEXT: lxv vs0, 0(r5)
; CHECK-BE-NEXT: lxv v3, 16(r4)
; CHECK-BE-NEXT: pmdmxvi8gerx4spp dmr0, vsp34, vs0, 100, 6, 12
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r6)
; CHECK-BE-NEXT: stxvp vsp34, 0(r6)
; CHECK-BE-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/dmr-enable.ll b/llvm/test/CodeGen/PowerPC/dmr-enable.ll
index 31c61190c0729..91b0e94cd2716 100644
--- a/llvm/test/CodeGen/PowerPC/dmr-enable.ll
+++ b/llvm/test/CodeGen/PowerPC/dmr-enable.ll
@@ -10,10 +10,10 @@ define void @tdmrz(ptr nocapture readonly %vp1, ptr nocapture %resp) {
; CHECK-LABEL: tdmrz:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: dmsetdmrz dmr0
-; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r4)
; CHECK-NEXT: stxvp vsp36, 64(r4)
-; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r4)
; CHECK-NEXT: stxvp vsp36, 0(r4)
; CHECK-NEXT: blr
@@ -21,10 +21,10 @@ define void @tdmrz(ptr nocapture readonly %vp1, ptr nocapture %resp) {
; CHECK-BE-LABEL: tdmrz:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: dmsetdmrz dmr0
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r4)
; CHECK-BE-NEXT: stxvp vsp34, 64(r4)
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r4)
; CHECK-BE-NEXT: stxvp vsp34, 0(r4)
; CHECK-BE-NEXT: blr
@@ -44,10 +44,10 @@ define void @tdmmr(ptr nocapture readonly %vp1, ptr nocapture %resp) {
; CHECK-NEXT: lxvp vsp36, 96(r3)
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
; CHECK-NEXT: dmmr dmr0, dmr0
-; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r4)
; CHECK-NEXT: stxvp vsp36, 64(r4)
-; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r4)
; CHECK-NEXT: stxvp vsp36, 0(r4)
; CHECK-NEXT: blr
@@ -61,10 +61,10 @@ define void @tdmmr(ptr nocapture readonly %vp1, ptr nocapture %resp) {
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmmr dmr0, dmr0
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r4)
; CHECK-BE-NEXT: stxvp vsp34, 64(r4)
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r4)
; CHECK-BE-NEXT: stxvp vsp34, 0(r4)
; CHECK-BE-NEXT: blr
@@ -91,10 +91,10 @@ define void @tdmxor(ptr nocapture readonly %vp1, ptr %vp2, ptr nocapture %resp)
; CHECK-NEXT: lxvp vsp36, 96(r4)
; CHECK-NEXT: dmxxinstfdmr512 wacc1, vsp36, vsp34, 0
; CHECK-NEXT: dmxor dmr0, dmr1
-; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxvp vsp34, 96(r5)
; CHECK-NEXT: stxvp vsp36, 64(r5)
-; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-NEXT: stxvp vsp34, 32(r5)
; CHECK-NEXT: stxvp vsp36, 0(r5)
; CHECK-NEXT: blr
@@ -114,10 +114,10 @@ define void @tdmxor(ptr nocapture readonly %vp1, ptr %vp2, ptr nocapture %resp)
; CHECK-BE-NEXT: lxvp vsp36, 0(r4)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc1, vsp36, vsp34, 0
; CHECK-BE-NEXT: dmxor dmr0, dmr1
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
; CHECK-BE-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll b/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll
index 5ca8c7b02cab4..c83ad73e00eda 100644
--- a/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll
+++ b/llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll
@@ -37,7 +37,7 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-NEXT: ld r30, 272(r1)
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp60, vsp62, 0
; CHECK-NEXT: xvf16ger2pp wacc0, v2, v4
-; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc0, 0
; CHECK-NEXT: stxvp vsp36, 64(r1)
; CHECK-NEXT: stxvp vsp34, 32(r1)
; CHECK-NEXT: bl foo at notoc
@@ -45,7 +45,7 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-NEXT: lxvp vsp36, 32(r1)
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
; CHECK-NEXT: xvf16ger2pp wacc0, v28, v30
-; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxv v4, 48(r30)
; CHECK-NEXT: stxv v5, 32(r30)
; CHECK-NEXT: stxv v2, 16(r30)
@@ -84,7 +84,7 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-BE-NEXT: ld r30, 368(r1)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp60, vsp62, 0
; CHECK-BE-NEXT: xvf16ger2pp wacc0, v2, v4
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp36, vsp34, 0
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc0, 0
; CHECK-BE-NEXT: stxvp vsp36, 112(r1)
; CHECK-BE-NEXT: stxvp vsp34, 144(r1)
; CHECK-BE-NEXT: bl foo
@@ -93,7 +93,7 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
; CHECK-BE-NEXT: lxvp vsp36, 144(r1)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
; CHECK-BE-NEXT: xvf16ger2pp wacc0, v28, v30
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxv v5, 48(r30)
; CHECK-BE-NEXT: stxv v4, 32(r30)
; CHECK-BE-NEXT: stxv v3, 16(r30)
diff --git a/llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll b/llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll
index 84ce324bfde7f..31631d3f92d8f 100644
--- a/llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll
@@ -30,7 +30,7 @@ define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmr v3, v2
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
-; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxv v4, 48(r3)
; CHECK-NEXT: stxv v5, 32(r3)
; CHECK-NEXT: stxv v2, 16(r3)
@@ -41,7 +41,7 @@ define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vmr v3, v2
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxv v5, 48(r3)
; CHECK-BE-NEXT: stxv v4, 32(r3)
; CHECK-BE-NEXT: stxv v3, 16(r3)
@@ -55,7 +55,7 @@ define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
; CHECK-O0-NEXT: vmr v3, v4
; CHECK-O0-NEXT: vmr v2, v4
; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
-; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-O0-NEXT: xxlor vs0, v4, v4
; CHECK-O0-NEXT: stxv vs0, 48(r3)
; CHECK-O0-NEXT: xxlor vs0, v5, v5
@@ -73,7 +73,7 @@ define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
; CHECK-O0-BE-NEXT: vmr v3, v4
; CHECK-O0-BE-NEXT: vmr v2, v4
; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
-; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
; CHECK-O0-BE-NEXT: stxv vs0, 48(r3)
; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
@@ -88,7 +88,7 @@ define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
; CHECK-AIX64: # %bb.0: # %entry
; CHECK-AIX64-NEXT: vmr 3, 2
; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 34, 34, 0
-; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
+; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 0
; CHECK-AIX64-NEXT: stxv 5, 48(3)
; CHECK-AIX64-NEXT: stxv 4, 32(3)
; CHECK-AIX64-NEXT: stxv 3, 16(3)
@@ -99,7 +99,7 @@ define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
; CHECK-AIX32: # %bb.0: # %entry
; CHECK-AIX32-NEXT: vmr 3, 2
; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 34, 34, 0
-; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
+; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0
; CHECK-AIX32-NEXT: stxv 5, 48(3)
; CHECK-AIX32-NEXT: stxv 4, 32(3)
; CHECK-AIX32-NEXT: stxv 3, 16(3)
@@ -120,7 +120,7 @@ define void @ld_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-NEXT: lxv v2, 16(r3)
; CHECK-NEXT: lxv v4, 48(r3)
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
-; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-NEXT: stxv v4, 48(r7)
; CHECK-NEXT: stxv v5, 32(r7)
; CHECK-NEXT: stxv v2, 16(r7)
@@ -134,7 +134,7 @@ define void @ld_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-BE-NEXT: lxv v2, 32(r3)
; CHECK-BE-NEXT: lxv v4, 0(r3)
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
-; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-BE-NEXT: stxv v5, 48(r7)
; CHECK-BE-NEXT: stxv v4, 32(r7)
; CHECK-BE-NEXT: stxv v3, 16(r7)
@@ -154,7 +154,7 @@ define void @ld_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-O0-NEXT: lxv vs0, 48(r3)
; CHECK-O0-NEXT: xxlor v2, vs0, vs0
; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
-; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-O0-NEXT: xxlor vs0, v4, v4
; CHECK-O0-NEXT: stxv vs0, 48(r7)
; CHECK-O0-NEXT: xxlor vs0, v5, v5
@@ -178,7 +178,7 @@ define void @ld_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)
; CHECK-O0-BE-NEXT: xxlor v2, vs0, vs0
; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
-; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
+; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
; CHECK-O0-BE-NEXT: stxv vs0, 48(r7)
; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
@@ -196,7 +196,7 @@ define void @ld_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {
; CHECK-AIX64-NEXT: lxv 2, 32(3)
; CHECK-AIX64-NEXT: lxv 4, 0(3)
; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 3...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/132083
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