[llvm] [Target] Use DenseSet instead of DenseMap (NFC) (PR #132619)

[Kazu Hirata via llvm-commits]

https://github.com/kazutakahirata created https://github.com/llvm/llvm-project/pull/132619

This patch uses DenseSet instead of DenseMap.  Note that the set of
Registers that map to true without this patch is the same as the set
of Registers that are present in the set with this patch.  This patch
is inspired by:

  commit d7879e524fbbc4c2790dac62343444191f736f00
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   Wed Mar 19 08:32:09 2025 -0700


>From 6a29c605131f57c13447c29f8a3d4e5aca607048 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu at google.com>
Date: Wed, 19 Mar 2025 01:00:31 -0700
Subject: [PATCH] [Target] Use DenseSet instead of DenseMap (NFC)

This patch uses DenseSet instead of DenseMap.  Note that the set of
Registers that map to true without this patch is the same as the set
of Registers that are present in the set with this patch.  This patch
is inspired by:

  commit d7879e524fbbc4c2790dac62343444191f736f00
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   Wed Mar 19 08:32:09 2025 -0700
---
 llvm/lib/Target/VE/VEISelLowering.cpp   | 6 +++---
 llvm/lib/Target/X86/X86ISelLowering.cpp | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index b7fa089921c2d..313c894cafa85 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -2645,15 +2645,15 @@ VETargetLowering::emitSjLjDispatchBlock(MachineInstr &MI,
       if (!II.isCall())
         continue;
 
-      DenseMap<Register, bool> DefRegs;
+      DenseSet<Register> DefRegs;
       for (auto &MOp : II.operands())
         if (MOp.isReg())
-          DefRegs[MOp.getReg()] = true;
+          DefRegs.insert(MOp.getReg());
 
       MachineInstrBuilder MIB(*MF, &II);
       for (unsigned RI = 0; SavedRegs[RI]; ++RI) {
         Register Reg = SavedRegs[RI];
-        if (!DefRegs[Reg])
+        if (!DefRegs.contains(Reg))
           MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
       }
 
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a7db154bfaa3b..0f737b1f8d854 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -37430,15 +37430,15 @@ X86TargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
       if (!II.isCall())
         continue;
 
-      DenseMap<Register, bool> DefRegs;
+      DenseSet<Register> DefRegs;
       for (auto &MOp : II.operands())
         if (MOp.isReg())
-          DefRegs[MOp.getReg()] = true;
+          DefRegs.insert(MOp.getReg());
 
       MachineInstrBuilder MIB(*MF, &II);
       for (unsigned RegIdx = 0; SavedRegs[RegIdx]; ++RegIdx) {
         Register Reg = SavedRegs[RegIdx];
-        if (!DefRegs[Reg])
+        if (!DefRegs.contains(Reg))
           MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
       }