[llvm] [ARM] Use DenseSet instead of DenseMap. NFC (PR #131978)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/131978

The value in the map is set to "true" when something is added to the map.

Techncally this:

  if (!DefRegs.contains(Reg))

will set the value in the map to false if it didn't alrady exist, and this is used to indicate the value wasn't in the map. This only occurs after all the "true" values have already been added to the map.

>From 35ecb050093af2d0d5a98753cdbd2009513a392a Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 18 Mar 2025 23:05:48 -0700
Subject: [PATCH] [ARM] Use DenseSet instead of DenseMap. NFC

The value in the map is set to "true" when something is added to
the map.

Techncally this:

  if (!DefRegs.contains(Reg))

will set the value in the map to false if it didn't alrady exist,
and this is used to indicate the value wasn't in the map. This only
occurs after all the "true" values have already been added to the map.
---
 llvm/lib/Target/ARM/ARMISelLowering.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 1fb68fa85f7b6..234abefe75ee7 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -11366,12 +11366,12 @@ void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
            II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
       if (!II->isCall()) continue;
 
-      DenseMap<unsigned, bool> DefRegs;
+      DenseSet<unsigned> DefRegs;
       for (MachineInstr::mop_iterator
              OI = II->operands_begin(), OE = II->operands_end();
            OI != OE; ++OI) {
         if (!OI->isReg()) continue;
-        DefRegs[OI->getReg()] = true;
+        DefRegs.insert(OI->getReg());
       }
 
       MachineInstrBuilder MIB(*MF, &*II);
@@ -11386,7 +11386,7 @@ void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
           continue;
         if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
           continue;
-        if (!DefRegs[Reg])
+        if (!DefRegs.contains(Reg))
           MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
       }