[llvm] [RISCV] Add combine for shadd family of instructions. (PR #130829)

[Craig Topper via llvm-commits]

================
@@ -14306,6 +14313,84 @@ static SDValue transformAddShlImm(SDNode *N, SelectionDAG &DAG,
   return DAG.getNode(ISD::SHL, DL, VT, SHADD, DAG.getConstant(Bits, DL, VT));
 }
 
+// Check if this SDValue is an add immediate that is fed by a shift of 1, 2,
+// or 3.
+static bool checkAddiForShift(SDValue AddI, int64_t &AddConst,
+                              int64_t &ShlConst) {
+  using namespace llvm::SDPatternMatch;
+  // Based on testing it seems that performance degrades if the ADDI has
+  // more than 2 uses.
+  if (AddI->use_size() > 2)
+    return false;
+
+  APInt AddVal;
+  SDValue SHLVal;
+  assert(sd_match(AddI, m_Add(m_Value(SHLVal), m_ConstInt(AddVal))) &&
+         "Expected an addi with a constant addition.");
+
+  APInt VShift;
+  if (!sd_match(SHLVal, m_BinOp(ISD::SHL, m_Value(), m_ConstInt(VShift))))
+    return false;
+
+  if (VShift.slt(1) || VShift.sgt(3))
+    return false;
+
+  // Set the values at the end when we know that the function will return
+  // true.
+  ShlConst = VShift.getSExtValue();
+  AddConst = AddVal.getSExtValue();
+  return true;
+}
+
+// Optimize (add (add (shl x, c0),  c1), y) ->
+//          (ADDI (SH*ADD y, x), c1), if c0 equals to [1|2|3].
+static SDValue combineShlAddIAdd(SDNode *N, SelectionDAG &DAG,
+                                 const RISCVSubtarget &Subtarget) {
+  using namespace llvm::SDPatternMatch;
+
+  // Perform this optimization only in the zba extension.
+  if (!ReassocShlAddiAdd || !Subtarget.hasStdExtZba())
+    return SDValue();
+
+  // Skip for vector types and larger types.
+  EVT VT = N->getValueType(0);
+  if (VT != Subtarget.getXLenVT())
+    return SDValue();
+
+  // Looking for a reg-reg add and not an addi.
+  if (isa<ConstantSDNode>(N->getOperand(1)))
+    return SDValue();
+
+  SDValue AddI = N->getOperand(0);
+  SDValue Other = N->getOperand(1);
+  bool LHSIsAddI = sd_match(AddI, m_Add(m_Value(), m_ConstInt()));
----------------
topperc wrote:

Can we sink this into `checkAddiForShift` and rename it?

My thought is that we can do this to handle the commuting and put all the logic inside combineShlAddIAddImpl.

```
if (SDValue V = combineShlAddIAddImpl(N, N0, N1, DAG))
  return V;
if (SDValue V = combineShlAddIAddImpl(N, N1, N0, DAG))
  return V;
```

This is the structure we use for `combineSelectAndUseCommutative` and `combineOrOfCZERO`

https://github.com/llvm/llvm-project/pull/130829