[llvm] [RISCV] isLoadFromStackSlot and isStoreToStackSlot for vector spill/fill (PR #132296)

[Philip Reames via llvm-commits]

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@@ -99,6 +99,37 @@ Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
   return isLoadFromStackSlot(MI, FrameIndex, Dummy);
 }
 
+static std::optional<unsigned> getNFForRVVWholeLoadStore(unsigned Opcode) {
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preames wrote:

This was taken from the spec naming, but happy to switch it over.  I'd been sort hoping someone would tell me we already had a utility function for this I'd missed.  :)

https://github.com/llvm/llvm-project/pull/132296