[llvm] [AMDGPU] Fix register class constraints for si-fold-operands pass when folding immediate into copies (PR #131387)

[via llvm-commits]

================
@@ -1047,6 +1047,11 @@ void SIFoldOperandsImpl::foldOperand(
     if (MovOp == AMDGPU::COPY)
       return;
 
+    // Check if the destination register of the MOV operation belongs
+    // to a vector superclass. Folding would be illegal.
+    if (TRI->isVectorSuperClass(DestRC))
+      return;
----------------
mssefat wrote:


Thanks for your suggestion. Based on your comment, I've implemented the check. The snippet looks like following:

```
    // Check if the destination register class has a common class
    // with the expected register class for the MOV instruction.
    const MCInstrDesc &MovDesc = TII->get(MovOp);
    if (MovDesc.operands()[0].RegClass != -1) {
      const TargetRegisterClass *ResRC = 
          TRI->getRegClass(MovDesc.operands()[0].RegClass);
      const TargetRegisterClass *CommonRC = 
          TRI->getCommonSubClass(DestRC, ResRC);

      if (!CommonRC) {
        return;
      }
    }
```

Can you please confirm if this aligns correctly with your suggestion or further adjustments are needed?

https://github.com/llvm/llvm-project/pull/131387