[llvm] [SPIR-V] Add support for inline SPIR-V types (PR #125316)
Cassandra Beckley via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 18 11:53:32 PDT 2025
https://github.com/cassiebeckley updated https://github.com/llvm/llvm-project/pull/125316
>From 6c4ae27f24b00bb2a435957608059e5145c210d1 Mon Sep 17 00:00:00 2001
From: Cassandra Beckley <cbeckley at google.com>
Date: Wed, 20 Nov 2024 15:05:49 -0800
Subject: [PATCH 01/12] [SPIR-V] Add support for inline SPIR-V types
Using HLSL's [Inline
SPIR-V](https://microsoft.github.io/hlsl-specs/proposals/0011-inline-spirv.html)
features, users have the ability to use [`SpirvType`](https://microsoft.github.io/hlsl-specs/proposals/0011-inline-spirv.html#types)
to have fine-grained control over the SPIR-V representation of a type.
As explained in the spec, this is useful because it enables vendors to
author headers with types for their own extensions.
As discussed in [Target Extension Types for Inline SPIR-V and Decorated
Types](https://github.com/llvm/wg-hlsl/pull/105), we would like to
represent the HLSL SpirvType type using a 'spirv.Type' target
extension type in LLVM IR. This pull request lowers that type to SPIR-V.
---
llvm/lib/IR/Type.cpp | 20 +++
.../SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp | 31 +++++
.../SPIRV/MCTargetDesc/SPIRVInstPrinter.h | 1 +
.../SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp | 23 ++++
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 125 +++++++++++++-----
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 15 +++
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h | 5 +
llvm/lib/Target/SPIRV/SPIRVInstrFormats.td | 5 +
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 3 +
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 3 +-
llvm/test/CodeGen/SPIRV/inline/type.ll | 32 +++++
11 files changed, 230 insertions(+), 33 deletions(-)
create mode 100644 llvm/test/CodeGen/SPIRV/inline/type.ll
diff --git a/llvm/lib/IR/Type.cpp b/llvm/lib/IR/Type.cpp
index 277985b6b00a3..9a050bad1dfe2 100644
--- a/llvm/lib/IR/Type.cpp
+++ b/llvm/lib/IR/Type.cpp
@@ -968,6 +968,26 @@ static TargetTypeInfo getTargetTypeInfo(const TargetExtType *Ty) {
if (Name == "spirv.Image")
return TargetTypeInfo(PointerType::get(C, 0), TargetExtType::CanBeGlobal,
TargetExtType::CanBeLocal);
+ if (Name == "spirv.Type") {
+ assert(Ty->getNumIntParameters() == 3 &&
+ "Wrong number of parameters for spirv.Type");
+
+ auto Size = Ty->getIntParameter(1);
+ auto Alignment = Ty->getIntParameter(2);
+
+ // LLVM expects variables that can be allocated to have an alignment and
+ // size. Default to using a 32-bit int as the layout type if none are
+ // present.
+ llvm::Type *LayoutType = Type::getInt32Ty(C);
+ if (Size > 0 && Alignment > 0)
+ LayoutType =
+ ArrayType::get(Type::getIntNTy(C, Alignment), Size * 8 / Alignment);
+
+ return TargetTypeInfo(LayoutType, TargetExtType::CanBeGlobal,
+ TargetExtType::CanBeLocal);
+ }
+ if (Name == "spirv.IntegralConstant" || Name == "spirv.Literal")
+ return TargetTypeInfo(Type::getVoidTy(C));
if (Name.starts_with("spirv."))
return TargetTypeInfo(PointerType::get(C, 0), TargetExtType::HasZeroInit,
TargetExtType::CanBeGlobal,
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
index 2ee0c79b8f7c1..136949d1116b2 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
@@ -116,6 +116,8 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
recordOpExtInstImport(MI);
} else if (OpCode == SPIRV::OpExtInst) {
printOpExtInst(MI, OS);
+ } else if (OpCode == SPIRV::UNKNOWN_type) {
+ printUnknownType(MI, OS);
} else {
// Print any extra operands for variadic instructions.
const MCInstrDesc &MCDesc = MII.get(OpCode);
@@ -314,6 +316,35 @@ void SPIRVInstPrinter::printOpDecorate(const MCInst *MI, raw_ostream &O) {
}
}
+void SPIRVInstPrinter::printUnknownType(const MCInst *MI, raw_ostream &O) {
+ const auto EnumOperand = MI->getOperand(1);
+ assert(EnumOperand.isImm() &&
+ "second operand of UNKNOWN_type must be opcode!");
+
+ const auto Enumerant = EnumOperand.getImm();
+ const auto NumOps = MI->getNumOperands();
+
+ // Encode the instruction enumerant and word count into the opcode
+ const auto OpCode = (0xFF & NumOps) << 16 | (0xFF & Enumerant);
+
+ // Print the opcode using the spirv-as arbitrary integer syntax
+ // https://github.com/KhronosGroup/SPIRV-Tools/blob/main/docs/syntax.md#arbitrary-integers
+ O << "!0x" << Twine::utohexstr(OpCode) << " ";
+
+ // The result ID must be printed after the opcode when using this syntax
+ printOperand(MI, 0, O);
+
+ O << " ";
+
+ const MCInstrDesc &MCDesc = MII.get(MI->getOpcode());
+ unsigned NumFixedOps = MCDesc.getNumOperands();
+ if (NumOps == NumFixedOps)
+ return;
+
+ // Print the rest of the operands
+ printRemainingVariableOps(MI, NumFixedOps, O, true);
+}
+
static void printExpr(const MCExpr *Expr, raw_ostream &O) {
#ifndef NDEBUG
const MCSymbolRefExpr *SRE;
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.h b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.h
index 9b02524f50b81..a7b38a6951c51 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.h
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.h
@@ -35,6 +35,7 @@ class SPIRVInstPrinter : public MCInstPrinter {
void printOpDecorate(const MCInst *MI, raw_ostream &O);
void printOpExtInst(const MCInst *MI, raw_ostream &O);
+ void printUnknownType(const MCInst *MI, raw_ostream &O);
void printRemainingVariableOps(const MCInst *MI, unsigned StartIndex,
raw_ostream &O, bool SkipFirstSpace = false,
bool SkipImmediates = false);
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
index 68cc6a3a7aac1..9f2b74c29a93b 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
@@ -46,6 +46,9 @@ class SPIRVMCCodeEmitter : public MCCodeEmitter {
void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
+ void encodeUnknownType(const MCInst &MI, SmallVectorImpl<char> &CB,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
};
} // end anonymous namespace
@@ -104,10 +107,30 @@ static void emitUntypedInstrOperands(const MCInst &MI,
emitOperand(Op, CB);
}
+void SPIRVMCCodeEmitter::encodeUnknownType(const MCInst &MI,
+ SmallVectorImpl<char> &CB,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ // Encode the first 32 SPIR-V bytes with the number of args and the opcode.
+ const uint64_t OpCode = MI.getOperand(1).getImm();
+ const uint32_t NumWords = MI.getNumOperands();
+ const uint32_t FirstWord = (NumWords << 16) | OpCode;
+ support::endian::write(CB, FirstWord, llvm::endianness::little);
+
+ emitOperand(MI.getOperand(0), CB);
+ for (unsigned i = 2; i < NumWords; ++i)
+ emitOperand(MI.getOperand(i), CB);
+}
+
void SPIRVMCCodeEmitter::encodeInstruction(const MCInst &MI,
SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
+ if (MI.getOpcode() == SPIRV::UNKNOWN_type) {
+ encodeUnknownType(MI, CB, Fixups, STI);
+ return;
+ }
+
// Encode the first 32 SPIR-V bytes with the number of args and the opcode.
const uint64_t OpCode = getBinaryCodeForInstr(MI, Fixups, STI);
const uint32_t NumWords = MI.getNumOperands() + 1;
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 95fa7bc3894fd..58822e5279b2d 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -2868,6 +2868,61 @@ static SPIRVType *getSampledImageType(const TargetExtType *OpaqueType,
return GR->getOrCreateOpTypeSampledImage(OpaqueImageType, MIRBuilder);
}
+static SPIRVType *getInlineSpirvType(const TargetExtType *ExtensionType,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ assert(ExtensionType->getNumIntParameters() == 3 &&
+ "Inline SPIR-V type builtin takes an opcode, size, and alignment "
+ "parameter");
+ auto Opcode = ExtensionType->getIntParameter(0);
+
+ return GR->getOrCreateUnknownType(
+ ExtensionType, MIRBuilder, Opcode,
+ [&ExtensionType, &GR, &MIRBuilder](llvm::MachineInstrBuilder Instr) {
+ for (llvm::Type *Param : ExtensionType->type_params()) {
+ if (const TargetExtType *ParamEType =
+ dyn_cast<TargetExtType>(Param)) {
+ if (ParamEType->getName() == "spirv.IntegralConstant") {
+ assert(ParamEType->getNumTypeParameters() == 1 &&
+ "Inline SPIR-V integral constant builtin must have a type "
+ "parameter");
+ assert(ParamEType->getNumIntParameters() == 1 &&
+ "Inline SPIR-V integral constant builtin must have a "
+ "value parameter");
+
+ auto OperandValue = ParamEType->getIntParameter(0);
+ auto *OperandType = ParamEType->getTypeParameter(0);
+
+ const SPIRVType *OperandSPIRVType =
+ GR->getOrCreateSPIRVType(OperandType, MIRBuilder);
+
+ Instr = Instr.addUse(GR->buildConstantInt(
+ OperandValue, MIRBuilder, OperandSPIRVType, true));
+ continue;
+ } else if (ParamEType->getName() == "spirv.Literal") {
+ assert(ParamEType->getNumTypeParameters() == 0 &&
+ "Inline SPIR-V literal builtin does not take type "
+ "parameters");
+ assert(ParamEType->getNumIntParameters() == 1 &&
+ "Inline SPIR-V literal builtin must have an integer "
+ "parameter");
+
+ auto OperandValue = ParamEType->getIntParameter(0);
+
+ Instr = Instr.addImm(OperandValue);
+ continue;
+ }
+ }
+ const SPIRVType *TypeOperand =
+ GR->getOrCreateSPIRVType(Param, MIRBuilder);
+ Instr = Instr.addUse(GR->getSPIRVTypeID(TypeOperand));
+ }
+ return Instr;
+ });
+
+ // GR->getOrCreateSPIRVArrayType();
+}
+
namespace SPIRV {
TargetExtType *parseBuiltinTypeNameToTargetExtType(std::string TypeName,
LLVMContext &Context) {
@@ -2940,39 +2995,45 @@ SPIRVType *lowerBuiltinType(const Type *OpaqueType,
const StringRef Name = BuiltinType->getName();
LLVM_DEBUG(dbgs() << "Lowering builtin type: " << Name << "\n");
- // Lookup the demangled builtin type in the TableGen records.
- const SPIRV::BuiltinType *TypeRecord = SPIRV::lookupBuiltinType(Name);
- if (!TypeRecord)
- report_fatal_error("Missing TableGen record for builtin type: " + Name);
-
- // "Lower" the BuiltinType into TargetType. The following get<...>Type methods
- // use the implementation details from TableGen records or TargetExtType
- // parameters to either create a new OpType<...> machine instruction or get an
- // existing equivalent SPIRVType from GlobalRegistry.
SPIRVType *TargetType;
- switch (TypeRecord->Opcode) {
- case SPIRV::OpTypeImage:
- TargetType = getImageType(BuiltinType, AccessQual, MIRBuilder, GR);
- break;
- case SPIRV::OpTypePipe:
- TargetType = getPipeType(BuiltinType, MIRBuilder, GR);
- break;
- case SPIRV::OpTypeDeviceEvent:
- TargetType = GR->getOrCreateOpTypeDeviceEvent(MIRBuilder);
- break;
- case SPIRV::OpTypeSampler:
- TargetType = getSamplerType(MIRBuilder, GR);
- break;
- case SPIRV::OpTypeSampledImage:
- TargetType = getSampledImageType(BuiltinType, MIRBuilder, GR);
- break;
- case SPIRV::OpTypeCooperativeMatrixKHR:
- TargetType = getCoopMatrType(BuiltinType, MIRBuilder, GR);
- break;
- default:
- TargetType =
- getNonParameterizedType(BuiltinType, TypeRecord, MIRBuilder, GR);
- break;
+ if (Name == "spirv.Type") {
+ TargetType = getInlineSpirvType(BuiltinType, MIRBuilder, GR);
+ } else {
+ // Lookup the demangled builtin type in the TableGen records.
+ const SPIRV::BuiltinType *TypeRecord = SPIRV::lookupBuiltinType(Name);
+ if (!TypeRecord)
+ report_fatal_error("Missing TableGen record for builtin type: " + Name);
+
+ // "Lower" the BuiltinType into TargetType. The following get<...>Type
+ // methods use the implementation details from TableGen records or
+ // TargetExtType parameters to either create a new OpType<...> machine
+ // instruction or get an existing equivalent SPIRVType from
+ // GlobalRegistry.
+
+ switch (TypeRecord->Opcode) {
+ case SPIRV::OpTypeImage:
+ TargetType = getImageType(BuiltinType, AccessQual, MIRBuilder, GR);
+ break;
+ case SPIRV::OpTypePipe:
+ TargetType = getPipeType(BuiltinType, MIRBuilder, GR);
+ break;
+ case SPIRV::OpTypeDeviceEvent:
+ TargetType = GR->getOrCreateOpTypeDeviceEvent(MIRBuilder);
+ break;
+ case SPIRV::OpTypeSampler:
+ TargetType = getSamplerType(MIRBuilder, GR);
+ break;
+ case SPIRV::OpTypeSampledImage:
+ TargetType = getSampledImageType(BuiltinType, MIRBuilder, GR);
+ break;
+ case SPIRV::OpTypeCooperativeMatrixKHR:
+ TargetType = getCoopMatrType(BuiltinType, MIRBuilder, GR);
+ break;
+ default:
+ TargetType =
+ getNonParameterizedType(BuiltinType, TypeRecord, MIRBuilder, GR);
+ break;
+ }
}
// Emit OpName instruction if a new OpType<...> instruction was added
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index e2f1b211caa5c..bb2e71e6870c1 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -1406,6 +1406,21 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeByOpcode(
return SpirvTy;
}
+SPIRVType *SPIRVGlobalRegistry::getOrCreateUnknownType(
+ const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode,
+ const std::function<llvm::MachineInstrBuilder(llvm::MachineInstrBuilder)>
+ &buildInstr) {
+ Register ResVReg = DT.find(Ty, &MIRBuilder.getMF());
+ if (ResVReg.isValid())
+ return MIRBuilder.getMF().getRegInfo().getUniqueVRegDef(ResVReg);
+ ResVReg = createTypeVReg(MIRBuilder);
+ SPIRVType *SpirvTy = buildInstr(MIRBuilder.buildInstr(SPIRV::UNKNOWN_type)
+ .addDef(ResVReg)
+ .addImm(Opcode));
+ DT.add(Ty, &MIRBuilder.getMF(), ResVReg);
+ return SpirvTy;
+}
+
const MachineInstr *
SPIRVGlobalRegistry::checkSpecialInstr(const SPIRV::SpecialTypeDescriptor &TD,
MachineIRBuilder &MIRBuilder) {
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
index 0c94ec4df97f5..d1fd05c31d7e3 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
@@ -618,6 +618,11 @@ class SPIRVGlobalRegistry {
MachineIRBuilder &MIRBuilder,
unsigned Opcode);
+ SPIRVType *getOrCreateUnknownType(
+ const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode,
+ const std::function<llvm::MachineInstrBuilder(llvm::MachineInstrBuilder)>
+ &buildInstr);
+
const TargetRegisterClass *getRegClass(SPIRVType *SpvType) const;
LLT getRegType(SPIRVType *SpvType) const;
};
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrFormats.td b/llvm/lib/Target/SPIRV/SPIRVInstrFormats.td
index 9451583a5fa85..2fde2b0bc0b1f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrFormats.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrFormats.td
@@ -25,6 +25,11 @@ class Op<bits<16> Opcode, dag outs, dag ins, string asmstr, list<dag> pattern =
let Pattern = pattern;
}
+class UnknownOp<dag outs, dag ins, string asmstr, list<dag> pattern = []>
+ : Op<0, outs, ins, asmstr, pattern> {
+ let isPseudo = 1;
+}
+
// Pseudo instructions
class Pseudo<dag outs, dag ins> : Op<0, outs, ins, ""> {
let isPseudo = 1;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 1bc35c6e57a4f..1fac9eec8d3bb 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -25,6 +25,9 @@ let isCodeGenOnly=1 in {
def GET_vpID: Pseudo<(outs vpID:$dst_id), (ins vpID:$src)>;
}
+def UNKNOWN_type
+ : UnknownOp<(outs TYPE:$type), (ins i32imm:$opcode, variable_ops), " ">;
+
def SPVTypeBin : SDTypeProfile<1, 2, []>;
def assigntype : SDNode<"SPIRVISD::AssignType", SPVTypeBin>;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index e7d8fe5bd8015..01c0e0b24bfce 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -495,7 +495,8 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) {
bool HasDefs = I.getNumDefs() > 0;
Register ResVReg = HasDefs ? I.getOperand(0).getReg() : Register(0);
SPIRVType *ResType = HasDefs ? GR.getSPIRVTypeForVReg(ResVReg) : nullptr;
- assert(!HasDefs || ResType || I.getOpcode() == TargetOpcode::G_GLOBAL_VALUE);
+ assert(!HasDefs || ResType || I.getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
+ I.getOpcode() == TargetOpcode::G_IMPLICIT_DEF);
if (spvSelect(ResVReg, ResType, I)) {
if (HasDefs) // Make all vregs 64 bits (for SPIR-V IDs).
for (unsigned i = 0; i < I.getNumDefs(); ++i)
diff --git a/llvm/test/CodeGen/SPIRV/inline/type.ll b/llvm/test/CodeGen/SPIRV/inline/type.ll
new file mode 100644
index 0000000000000..c723b2902bec1
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/inline/type.ll
@@ -0,0 +1,32 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - | spirv-as - -o - | spirv-val %}
+
+; CHECK: [[uint32_t:%[0-9]+]] = OpTypeInt 32 0
+
+; CHECK: [[image_t:%[0-9]+]] = OpTypeImage %3 2D 2 0 0 1 Unknown
+%type_2d_image = type target("spirv.Image", float, 1, 2, 0, 0, 1, 0)
+
+%literal_false = type target("spirv.Literal", 0)
+%literal_8 = type target("spirv.Literal", 8)
+
+; CHECK: [[uint32_4:%[0-9]+]] = OpConstant [[uint32_t]] 4
+%integral_constant_4 = type target("spirv.IntegralConstant", i32, 4)
+
+; CHECK: !0x4001c [[array_t:%[0-9]+]] [[image_t]] [[uint32_4]]
+%ArrayTex2D = type target("spirv.Type", %type_2d_image, %integral_constant_4, 28, 0, 0)
+
+; CHECK: [[getTexArray_t:%[0-9]+]] = OpTypeFunction [[array_t]]
+
+; CHECK: [[getTexArray:%[0-9]+]] = OpFunction [[array_t]] None [[getTexArray_t]]
+declare %ArrayTex2D @getTexArray()
+
+define void @main() #1 {
+entry:
+ %images = alloca %ArrayTex2D
+
+; CHECK: {{%[0-9]+}} = OpFunctionCall [[array_t]] [[getTexArray]]
+ %retTex = call %ArrayTex2D @getTexArray()
+
+ ret void
+}
>From 10b18e109ca7000994906427a236d30e02dad115 Mon Sep 17 00:00:00 2001
From: Cassandra Beckley <cbeckley at google.com>
Date: Mon, 3 Feb 2025 14:32:23 -0800
Subject: [PATCH 02/12] Remove commented-out code; add integer/literal test
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 2 --
llvm/test/CodeGen/SPIRV/inline/type.ll | 15 +++++++++++++--
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 58822e5279b2d..69b9dea980ee5 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -2919,8 +2919,6 @@ static SPIRVType *getInlineSpirvType(const TargetExtType *ExtensionType,
}
return Instr;
});
-
- // GR->getOrCreateSPIRVArrayType();
}
namespace SPIRV {
diff --git a/llvm/test/CodeGen/SPIRV/inline/type.ll b/llvm/test/CodeGen/SPIRV/inline/type.ll
index c723b2902bec1..c75b6dec2fa68 100644
--- a/llvm/test/CodeGen/SPIRV/inline/type.ll
+++ b/llvm/test/CodeGen/SPIRV/inline/type.ll
@@ -7,8 +7,8 @@
; CHECK: [[image_t:%[0-9]+]] = OpTypeImage %3 2D 2 0 0 1 Unknown
%type_2d_image = type target("spirv.Image", float, 1, 2, 0, 0, 1, 0)
-%literal_false = type target("spirv.Literal", 0)
-%literal_8 = type target("spirv.Literal", 8)
+%literal_true = type target("spirv.Literal", 1)
+%literal_32 = type target("spirv.Literal", 32)
; CHECK: [[uint32_4:%[0-9]+]] = OpConstant [[uint32_t]] 4
%integral_constant_4 = type target("spirv.IntegralConstant", i32, 4)
@@ -18,9 +18,17 @@
; CHECK: [[getTexArray_t:%[0-9]+]] = OpTypeFunction [[array_t]]
+; CHECK: !0x40015 [[int_t:%[0-9]+]] 32 1
+%int_t = type target("spirv.Type", %literal_32, %literal_true, 21, 0, 0)
+
+; CHECK: [[getInt_t:%[0-9]+]] = OpTypeFunction [[int_t]]
+
; CHECK: [[getTexArray:%[0-9]+]] = OpFunction [[array_t]] None [[getTexArray_t]]
declare %ArrayTex2D @getTexArray()
+; CHECK: [[getInt:%[0-9]+]] = OpFunction [[int_t]] None [[getInt_t]]
+declare %int_t @getInt()
+
define void @main() #1 {
entry:
%images = alloca %ArrayTex2D
@@ -28,5 +36,8 @@ entry:
; CHECK: {{%[0-9]+}} = OpFunctionCall [[array_t]] [[getTexArray]]
%retTex = call %ArrayTex2D @getTexArray()
+; CHECK: {{%[0-9]+}} = OpFunctionCall [[int_t]] [[getInt]]
+ %i = call %int_t @getInt()
+
ret void
}
>From 478d3b7f631c6b4bfaf40c8f1c26fd240f2efdbc Mon Sep 17 00:00:00 2001
From: Cassandra Beckley <cbeckley at google.com>
Date: Tue, 4 Feb 2025 12:24:53 -0800
Subject: [PATCH 03/12] Add documentation for inline SPIR-V types
---
llvm/docs/SPIRVUsage.rst | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index b7601b26beb89..7e526450826ff 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -260,6 +260,28 @@ parameters of its underlying image type, so that a sampled image for the
previous type has the representation
``target("spirv.SampledImage, void, 1, 1, 0, 0, 0, 0, 0)``.
+.. _inline-spirv-types:
+
+Inline SPIR-V Types
+-------------------
+
+User-specified types may be represented using target extension types:
+
+ .. table:: Inline SPIR-V Types
+
+ ========================== =================== ==============================
+ LLVM type name LLVM type arguments LLVM integer arguments
+ ========================== =================== ==============================
+ ``spirv.Type`` SPIR-V operands opcode, size, alignment
+ ``spirv.IntegralConstant`` integral type value
+ ``spirv.Literal`` (none) value
+ ========================== =================== ==============================
+
+The operand arguments to ``spirv.Type`` may be either a ``spirv.IntegralConstant`` type,
+representing an ``OpConstant`` id operand, a ``spirv.Literal`` type, representing an immediate
+literal operand, or any other type, representing the id of that type as an operand.
+``spirv.IntegralConstant`` and ``spirv.Literal`` may not be used outside of this context.
+
.. _spirv-intrinsics:
Target Intrinsics
>From a3db639b840cbf24b29c20f0b35316cd6a2bf0c4 Mon Sep 17 00:00:00 2001
From: Cassandra Beckley <cbeckley at google.com>
Date: Wed, 5 Feb 2025 09:15:30 -0800
Subject: [PATCH 04/12] Try empty commit to re-push to GitHub
>From d731b2ea36156d1c66703f6acc4c97447988763b Mon Sep 17 00:00:00 2001
From: Cassandra Beckley <cbeckley at google.com>
Date: Fri, 7 Feb 2025 16:39:13 -0800
Subject: [PATCH 05/12] Replace lambda with list of operands
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 83 +++++++++----------
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 19 +++--
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h | 8 +-
3 files changed, 57 insertions(+), 53 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 69b9dea980ee5..66f96d793eac9 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -2876,49 +2876,46 @@ static SPIRVType *getInlineSpirvType(const TargetExtType *ExtensionType,
"parameter");
auto Opcode = ExtensionType->getIntParameter(0);
- return GR->getOrCreateUnknownType(
- ExtensionType, MIRBuilder, Opcode,
- [&ExtensionType, &GR, &MIRBuilder](llvm::MachineInstrBuilder Instr) {
- for (llvm::Type *Param : ExtensionType->type_params()) {
- if (const TargetExtType *ParamEType =
- dyn_cast<TargetExtType>(Param)) {
- if (ParamEType->getName() == "spirv.IntegralConstant") {
- assert(ParamEType->getNumTypeParameters() == 1 &&
- "Inline SPIR-V integral constant builtin must have a type "
- "parameter");
- assert(ParamEType->getNumIntParameters() == 1 &&
- "Inline SPIR-V integral constant builtin must have a "
- "value parameter");
-
- auto OperandValue = ParamEType->getIntParameter(0);
- auto *OperandType = ParamEType->getTypeParameter(0);
-
- const SPIRVType *OperandSPIRVType =
- GR->getOrCreateSPIRVType(OperandType, MIRBuilder);
-
- Instr = Instr.addUse(GR->buildConstantInt(
- OperandValue, MIRBuilder, OperandSPIRVType, true));
- continue;
- } else if (ParamEType->getName() == "spirv.Literal") {
- assert(ParamEType->getNumTypeParameters() == 0 &&
- "Inline SPIR-V literal builtin does not take type "
- "parameters");
- assert(ParamEType->getNumIntParameters() == 1 &&
- "Inline SPIR-V literal builtin must have an integer "
- "parameter");
-
- auto OperandValue = ParamEType->getIntParameter(0);
-
- Instr = Instr.addImm(OperandValue);
- continue;
- }
- }
- const SPIRVType *TypeOperand =
- GR->getOrCreateSPIRVType(Param, MIRBuilder);
- Instr = Instr.addUse(GR->getSPIRVTypeID(TypeOperand));
- }
- return Instr;
- });
+ SmallVector<MCOperand> Operands;
+ for (llvm::Type *Param : ExtensionType->type_params()) {
+ if (const TargetExtType *ParamEType = dyn_cast<TargetExtType>(Param)) {
+ if (ParamEType->getName() == "spirv.IntegralConstant") {
+ assert(ParamEType->getNumTypeParameters() == 1 &&
+ "Inline SPIR-V integral constant builtin must have a type "
+ "parameter");
+ assert(ParamEType->getNumIntParameters() == 1 &&
+ "Inline SPIR-V integral constant builtin must have a "
+ "value parameter");
+
+ auto OperandValue = ParamEType->getIntParameter(0);
+ auto *OperandType = ParamEType->getTypeParameter(0);
+
+ const SPIRVType *OperandSPIRVType =
+ GR->getOrCreateSPIRVType(OperandType, MIRBuilder);
+
+ Operands.push_back(MCOperand::createReg(GR->buildConstantInt(
+ OperandValue, MIRBuilder, OperandSPIRVType, true)));
+ continue;
+ } else if (ParamEType->getName() == "spirv.Literal") {
+ assert(ParamEType->getNumTypeParameters() == 0 &&
+ "Inline SPIR-V literal builtin does not take type "
+ "parameters");
+ assert(ParamEType->getNumIntParameters() == 1 &&
+ "Inline SPIR-V literal builtin must have an integer "
+ "parameter");
+
+ auto OperandValue = ParamEType->getIntParameter(0);
+
+ Operands.push_back(MCOperand::createImm(OperandValue));
+ continue;
+ }
+ }
+ const SPIRVType *TypeOperand = GR->getOrCreateSPIRVType(Param, MIRBuilder);
+ Operands.push_back(MCOperand::createReg(GR->getSPIRVTypeID(TypeOperand)));
+ }
+
+ return GR->getOrCreateUnknownType(ExtensionType, MIRBuilder, Opcode,
+ Operands);
}
namespace SPIRV {
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index bb2e71e6870c1..77faf4b89c09e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -1408,17 +1408,24 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeByOpcode(
SPIRVType *SPIRVGlobalRegistry::getOrCreateUnknownType(
const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode,
- const std::function<llvm::MachineInstrBuilder(llvm::MachineInstrBuilder)>
- &buildInstr) {
+ const ArrayRef<MCOperand> Operands) {
Register ResVReg = DT.find(Ty, &MIRBuilder.getMF());
if (ResVReg.isValid())
return MIRBuilder.getMF().getRegInfo().getUniqueVRegDef(ResVReg);
ResVReg = createTypeVReg(MIRBuilder);
- SPIRVType *SpirvTy = buildInstr(MIRBuilder.buildInstr(SPIRV::UNKNOWN_type)
- .addDef(ResVReg)
- .addImm(Opcode));
+
+ MachineInstrBuilder MIB =
+ MIRBuilder.buildInstr(SPIRV::UNKNOWN_type).addDef(ResVReg).addImm(Opcode);
+ for (MCOperand Operand : Operands) {
+ if (Operand.isReg()) {
+ MIB.addUse(Operand.getReg());
+ } else if (Operand.isImm()) {
+ MIB.addImm(Operand.getImm());
+ }
+ }
+
DT.add(Ty, &MIRBuilder.getMF(), ResVReg);
- return SpirvTy;
+ return MIB;
}
const MachineInstr *
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
index d1fd05c31d7e3..925868f220343 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
@@ -618,10 +618,10 @@ class SPIRVGlobalRegistry {
MachineIRBuilder &MIRBuilder,
unsigned Opcode);
- SPIRVType *getOrCreateUnknownType(
- const Type *Ty, MachineIRBuilder &MIRBuilder, unsigned Opcode,
- const std::function<llvm::MachineInstrBuilder(llvm::MachineInstrBuilder)>
- &buildInstr);
+ SPIRVType *getOrCreateUnknownType(const Type *Ty,
+ MachineIRBuilder &MIRBuilder,
+ unsigned Opcode,
+ const ArrayRef<MCOperand> Operands);
const TargetRegisterClass *getRegClass(SPIRVType *SpvType) const;
LLT getRegType(SPIRVType *SpvType) const;
>From 78f9e7f26063d702c72414655ba0924ad56220c2 Mon Sep 17 00:00:00 2001
From: Cassandra Beckley <cbeckley at google.com>
Date: Fri, 7 Feb 2025 16:44:43 -0800
Subject: [PATCH 06/12] Encoding fixes
---
llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
index 9f2b74c29a93b..7008340010d13 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
@@ -114,7 +114,9 @@ void SPIRVMCCodeEmitter::encodeUnknownType(const MCInst &MI,
// Encode the first 32 SPIR-V bytes with the number of args and the opcode.
const uint64_t OpCode = MI.getOperand(1).getImm();
const uint32_t NumWords = MI.getNumOperands();
- const uint32_t FirstWord = (NumWords << 16) | OpCode;
+ const uint32_t FirstWord = (0xFF & NumWords) << 16 | (0xFF & OpCode);
+
+ // encoding: <opcode+len> <result type> [<operand0> <operand1> ...]
support::endian::write(CB, FirstWord, llvm::endianness::little);
emitOperand(MI.getOperand(0), CB);
>From a0403e7f0232fb318875676c5ebbb161b0343e89 Mon Sep 17 00:00:00 2001
From: Cassandra Beckley <cbeckley at google.com>
Date: Fri, 7 Feb 2025 16:51:11 -0800
Subject: [PATCH 07/12] Add link to HLSL spec
---
llvm/docs/SPIRVUsage.rst | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index 7e526450826ff..834328b7d1805 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -265,7 +265,11 @@ previous type has the representation
Inline SPIR-V Types
-------------------
-User-specified types may be represented using target extension types:
+HLSL allows users to create types representing specific SPIR-V types, using ``vk::SpirvType`` and
+``vk::SpirvOpaqueType``. These are specified in the `Inline SPIR-V`_ proposal. They may be
+represented using target extension types:
+
+.. _Inline SPIR-V: https://microsoft.github.io/hlsl-specs/proposals/0011-inline-spirv.html#types
.. table:: Inline SPIR-V Types
>From 8ce1a117fc143c4f65056a46c2cfb49deb762a89 Mon Sep 17 00:00:00 2001
From: Cassandra Beckley <cbeckley at google.com>
Date: Tue, 11 Feb 2025 14:37:59 -0800
Subject: [PATCH 08/12] Tentatively use proposed OpUnknown syntax
---
llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp | 5 ++---
llvm/test/CodeGen/SPIRV/inline/type.ll | 4 ++--
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
index 136949d1116b2..00534d65460f4 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
@@ -327,9 +327,8 @@ void SPIRVInstPrinter::printUnknownType(const MCInst *MI, raw_ostream &O) {
// Encode the instruction enumerant and word count into the opcode
const auto OpCode = (0xFF & NumOps) << 16 | (0xFF & Enumerant);
- // Print the opcode using the spirv-as arbitrary integer syntax
- // https://github.com/KhronosGroup/SPIRV-Tools/blob/main/docs/syntax.md#arbitrary-integers
- O << "!0x" << Twine::utohexstr(OpCode) << " ";
+ // Print the opcode using the spirv-as unknown opcode syntax
+ O << "OpUnknown(" << Enumerant << ", " << NumOps << ") ";
// The result ID must be printed after the opcode when using this syntax
printOperand(MI, 0, O);
diff --git a/llvm/test/CodeGen/SPIRV/inline/type.ll b/llvm/test/CodeGen/SPIRV/inline/type.ll
index c75b6dec2fa68..41675cf06e715 100644
--- a/llvm/test/CodeGen/SPIRV/inline/type.ll
+++ b/llvm/test/CodeGen/SPIRV/inline/type.ll
@@ -13,12 +13,12 @@
; CHECK: [[uint32_4:%[0-9]+]] = OpConstant [[uint32_t]] 4
%integral_constant_4 = type target("spirv.IntegralConstant", i32, 4)
-; CHECK: !0x4001c [[array_t:%[0-9]+]] [[image_t]] [[uint32_4]]
+; CHECK: OpUnknown(28, 4) [[array_t:%[0-9]+]] [[image_t]] [[uint32_4]]
%ArrayTex2D = type target("spirv.Type", %type_2d_image, %integral_constant_4, 28, 0, 0)
; CHECK: [[getTexArray_t:%[0-9]+]] = OpTypeFunction [[array_t]]
-; CHECK: !0x40015 [[int_t:%[0-9]+]] 32 1
+; CHECK: OpUnknown(21, 4) [[int_t:%[0-9]+]] 32 1
%int_t = type target("spirv.Type", %literal_32, %literal_true, 21, 0, 0)
; CHECK: [[getInt_t:%[0-9]+]] = OpTypeFunction [[int_t]]
>From 7c6757718e8ee55909aafb6cfbff046bbd9243ee Mon Sep 17 00:00:00 2001
From: Cassandra Beckley <cbeckley at google.com>
Date: Wed, 5 Mar 2025 16:08:57 -0800
Subject: [PATCH 09/12] Respond to feedback
---
llvm/docs/SPIRVUsage.rst | 22 +++++++++++++++
llvm/lib/IR/Type.cpp | 13 +++++----
.../SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp | 3 --
.../SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp | 4 +--
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 24 +++++++++-------
.../CodeGen/SPIRV/inline/type.coop-matrix.ll | 28 +++++++++++++++++++
llvm/test/CodeGen/SPIRV/inline/type.ll | 5 +---
7 files changed, 75 insertions(+), 24 deletions(-)
create mode 100644 llvm/test/CodeGen/SPIRV/inline/type.coop-matrix.ll
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index 834328b7d1805..b5167ef95711e 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -286,6 +286,28 @@ representing an ``OpConstant`` id operand, a ``spirv.Literal`` type, representin
literal operand, or any other type, representing the id of that type as an operand.
``spirv.IntegralConstant`` and ``spirv.Literal`` may not be used outside of this context.
+For example, ``OpTypeArray`` (opcode 28) takes an id for the element type and an id for the element
+length, so an array of 16 integers could be declared as:
+
+``target("spirv.Type", i32, target("spirv.IntegralConstant", i32, 16), 28, 64, 32)``
+
+This will be lowered to:
+
+``OpTypeArray %int %int_16``
+
+``OpTypeVector`` takes an id for the component type and a literal for the component count, so a
+4-integer vector could be declared as:
+
+``target("spirv.Type", i32, target("spirv.Literal", 4), 23, 16, 32)``
+
+This will be lowered to:
+
+``OpTypeVector %int 4``
+
+See `Target Extension Types for Inline SPIR-V and Decorated Types`_ for further details.
+
+.. _Target Extension Types for Inline SPIR-V and Decorated Types: https://github.com/llvm/wg-hlsl/blob/main/proposals/0017-inline-spirv-and-decorated-types.md
+
.. _spirv-intrinsics:
Target Intrinsics
diff --git a/llvm/lib/IR/Type.cpp b/llvm/lib/IR/Type.cpp
index 9a050bad1dfe2..a8a4fa8f6c065 100644
--- a/llvm/lib/IR/Type.cpp
+++ b/llvm/lib/IR/Type.cpp
@@ -975,13 +975,16 @@ static TargetTypeInfo getTargetTypeInfo(const TargetExtType *Ty) {
auto Size = Ty->getIntParameter(1);
auto Alignment = Ty->getIntParameter(2);
- // LLVM expects variables that can be allocated to have an alignment and
- // size. Default to using a 32-bit int as the layout type if none are
- // present.
- llvm::Type *LayoutType = Type::getInt32Ty(C);
- if (Size > 0 && Alignment > 0)
+ llvm::Type *LayoutType;
+ if (Size > 0 && Alignment > 0) {
LayoutType =
ArrayType::get(Type::getIntNTy(C, Alignment), Size * 8 / Alignment);
+ } else {
+ // LLVM expects variables that can be allocated to have an alignment and
+ // size. Default to using a 32-bit int as the layout type if none are
+ // present.
+ LayoutType = Type::getInt32Ty(C);
+ }
return TargetTypeInfo(LayoutType, TargetExtType::CanBeGlobal,
TargetExtType::CanBeLocal);
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
index 00534d65460f4..d113afdb5c0d3 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp
@@ -324,9 +324,6 @@ void SPIRVInstPrinter::printUnknownType(const MCInst *MI, raw_ostream &O) {
const auto Enumerant = EnumOperand.getImm();
const auto NumOps = MI->getNumOperands();
- // Encode the instruction enumerant and word count into the opcode
- const auto OpCode = (0xFF & NumOps) << 16 | (0xFF & Enumerant);
-
// Print the opcode using the spirv-as unknown opcode syntax
O << "OpUnknown(" << Enumerant << ", " << NumOps << ") ";
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
index 7008340010d13..145ccb53f9581 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
@@ -111,10 +111,10 @@ void SPIRVMCCodeEmitter::encodeUnknownType(const MCInst &MI,
SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
- // Encode the first 32 SPIR-V bytes with the number of args and the opcode.
+ // Encode the first 32 SPIR-V bits with the number of args and the opcode.
const uint64_t OpCode = MI.getOperand(1).getImm();
const uint32_t NumWords = MI.getNumOperands();
- const uint32_t FirstWord = (0xFF & NumWords) << 16 | (0xFF & OpCode);
+ const uint32_t FirstWord = (0xFFFF & NumWords) << 16 | (0xFFFF & OpCode);
// encoding: <opcode+len> <result type> [<operand0> <operand1> ...]
support::endian::write(CB, FirstWord, llvm::endianness::little);
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index 77faf4b89c09e..a6ca029b3fb39 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -1414,18 +1414,22 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateUnknownType(
return MIRBuilder.getMF().getRegInfo().getUniqueVRegDef(ResVReg);
ResVReg = createTypeVReg(MIRBuilder);
- MachineInstrBuilder MIB =
- MIRBuilder.buildInstr(SPIRV::UNKNOWN_type).addDef(ResVReg).addImm(Opcode);
- for (MCOperand Operand : Operands) {
- if (Operand.isReg()) {
- MIB.addUse(Operand.getReg());
- } else if (Operand.isImm()) {
- MIB.addImm(Operand.getImm());
+ DT.add(Ty, &MIRBuilder.getMF(), ResVReg);
+
+ return createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ MachineInstrBuilder MIB = MIRBuilder.buildInstr(SPIRV::UNKNOWN_type)
+ .addDef(ResVReg)
+ .addImm(Opcode);
+ for (MCOperand Operand : Operands) {
+ if (Operand.isReg()) {
+ MIB.addUse(Operand.getReg());
+ } else if (Operand.isImm()) {
+ MIB.addImm(Operand.getImm());
+ }
}
- }
- DT.add(Ty, &MIRBuilder.getMF(), ResVReg);
- return MIB;
+ return MIB;
+ });
}
const MachineInstr *
diff --git a/llvm/test/CodeGen/SPIRV/inline/type.coop-matrix.ll b/llvm/test/CodeGen/SPIRV/inline/type.coop-matrix.ll
new file mode 100644
index 0000000000000..3769c912a6fc8
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/inline/type.coop-matrix.ll
@@ -0,0 +1,28 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+
+; CHECK: [[float_t:%[0-9]+]] = OpTypeFloat 32
+; CHECK: [[uint32_t:%[0-9]+]] = OpTypeInt 32 0
+
+; CHECK: [[uint32_2:%[0-9]+]] = OpConstant [[uint32_t]] 2
+%scope = type target("spirv.IntegralConstant", i32, 2) ; Workgroup
+; CHECK: [[uint32_4:%[0-9]+]] = OpConstant [[uint32_t]] 4
+%cols = type target("spirv.IntegralConstant", i32, 4)
+%rows = type target("spirv.IntegralConstant", i32, 4)
+; CHECK: [[uint32_0:%[0-9]+]] = OpConstant [[uint32_t]] 0
+%use = type target("spirv.IntegralConstant", i32, 0) ; MatrixAKHR
+
+; CHECK: OpUnknown(4456, 7) [[coop_t:%[0-9]+]] [[float_t]] [[uint32_2]] [[uint32_4]] [[uint32_4]] [[uint32_0]]
+%coop_t = type target("spirv.Type", float, %scope, %rows, %cols, %use, 4456, 0, 0)
+
+; CHECK: [[getCooperativeMatrix_t:%[0-9]+]] = OpTypeFunction [[coop_t]]
+
+; CHECK: [[getCooperativeMatrix:%[0-9]+]] = OpFunction [[coop_t]] None [[getCooperativeMatrix_t]]
+declare %coop_t @getCooperativeMatrix()
+
+define void @main() #1 {
+entry:
+; CHECK: {{%[0-9]+}} = OpFunctionCall [[coop_t]] [[getCooperativeMatrix]]
+ %coop = call %coop_t @getCooperativeMatrix()
+
+ ret void
+}
diff --git a/llvm/test/CodeGen/SPIRV/inline/type.ll b/llvm/test/CodeGen/SPIRV/inline/type.ll
index 41675cf06e715..c9f1946d97048 100644
--- a/llvm/test/CodeGen/SPIRV/inline/type.ll
+++ b/llvm/test/CodeGen/SPIRV/inline/type.ll
@@ -16,11 +16,10 @@
; CHECK: OpUnknown(28, 4) [[array_t:%[0-9]+]] [[image_t]] [[uint32_4]]
%ArrayTex2D = type target("spirv.Type", %type_2d_image, %integral_constant_4, 28, 0, 0)
-; CHECK: [[getTexArray_t:%[0-9]+]] = OpTypeFunction [[array_t]]
-
; CHECK: OpUnknown(21, 4) [[int_t:%[0-9]+]] 32 1
%int_t = type target("spirv.Type", %literal_32, %literal_true, 21, 0, 0)
+; CHECK: [[getTexArray_t:%[0-9]+]] = OpTypeFunction [[array_t]]
; CHECK: [[getInt_t:%[0-9]+]] = OpTypeFunction [[int_t]]
; CHECK: [[getTexArray:%[0-9]+]] = OpFunction [[array_t]] None [[getTexArray_t]]
@@ -31,8 +30,6 @@ declare %int_t @getInt()
define void @main() #1 {
entry:
- %images = alloca %ArrayTex2D
-
; CHECK: {{%[0-9]+}} = OpFunctionCall [[array_t]] [[getTexArray]]
%retTex = call %ArrayTex2D @getTexArray()
>From 426bdc94159b0cd78f364ef1808ff5b8e9ae2470 Mon Sep 17 00:00:00 2001
From: Cassandra Beckley <cbeckley at google.com>
Date: Fri, 14 Mar 2025 09:25:53 -0700
Subject: [PATCH 10/12] Follow Nathan's feedback
---
llvm/lib/IR/Type.cpp | 2 +-
llvm/test/CodeGen/SPIRV/inline/type.coop-matrix.ll | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/IR/Type.cpp b/llvm/lib/IR/Type.cpp
index a8a4fa8f6c065..65b56fec78c2e 100644
--- a/llvm/lib/IR/Type.cpp
+++ b/llvm/lib/IR/Type.cpp
@@ -975,7 +975,7 @@ static TargetTypeInfo getTargetTypeInfo(const TargetExtType *Ty) {
auto Size = Ty->getIntParameter(1);
auto Alignment = Ty->getIntParameter(2);
- llvm::Type *LayoutType;
+ llvm::Type *LayoutType = nullptr;
if (Size > 0 && Alignment > 0) {
LayoutType =
ArrayType::get(Type::getIntNTy(C, Alignment), Size * 8 / Alignment);
diff --git a/llvm/test/CodeGen/SPIRV/inline/type.coop-matrix.ll b/llvm/test/CodeGen/SPIRV/inline/type.coop-matrix.ll
index 3769c912a6fc8..12effdfd464f1 100644
--- a/llvm/test/CodeGen/SPIRV/inline/type.coop-matrix.ll
+++ b/llvm/test/CodeGen/SPIRV/inline/type.coop-matrix.ll
@@ -1,5 +1,7 @@
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; TODO: enable spirv-val once we can add cooperative matrix capability and extension
+
; CHECK: [[float_t:%[0-9]+]] = OpTypeFloat 32
; CHECK: [[uint32_t:%[0-9]+]] = OpTypeInt 32 0
>From 798471674bdd63b5005fc738d4a27dfcf606734f Mon Sep 17 00:00:00 2001
From: Cassandra Beckley <cbeckley at google.com>
Date: Fri, 14 Mar 2025 09:48:19 -0700
Subject: [PATCH 11/12] Fix function call after merge
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 04877f7584383..058e9166d90c9 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -3063,8 +3063,8 @@ static SPIRVType *getInlineSpirvType(const TargetExtType *ExtensionType,
auto OperandValue = ParamEType->getIntParameter(0);
auto *OperandType = ParamEType->getTypeParameter(0);
- const SPIRVType *OperandSPIRVType =
- GR->getOrCreateSPIRVType(OperandType, MIRBuilder);
+ const SPIRVType *OperandSPIRVType = GR->getOrCreateSPIRVType(
+ OperandType, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, true);
Operands.push_back(MCOperand::createReg(GR->buildConstantInt(
OperandValue, MIRBuilder, OperandSPIRVType, true)));
@@ -3083,7 +3083,8 @@ static SPIRVType *getInlineSpirvType(const TargetExtType *ExtensionType,
continue;
}
}
- const SPIRVType *TypeOperand = GR->getOrCreateSPIRVType(Param, MIRBuilder);
+ const SPIRVType *TypeOperand = GR->getOrCreateSPIRVType(
+ Param, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, true);
Operands.push_back(MCOperand::createReg(GR->getSPIRVTypeID(TypeOperand)));
}
>From 4750fa33e90846b3b761cd526dc6459262c2ad9e Mon Sep 17 00:00:00 2001
From: Cassandra Beckley <cbeckley at google.com>
Date: Tue, 18 Mar 2025 11:51:41 -0700
Subject: [PATCH 12/12] Fix docs formatting
---
llvm/docs/SPIRVUsage.rst | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index a660fe9be0a56..2da3463f4bcef 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -279,13 +279,13 @@ represented using target extension types:
.. table:: Inline SPIR-V Types
- ========================== =================== ==============================
- LLVM type name LLVM type arguments LLVM integer arguments
- ========================== =================== ==============================
- ``spirv.Type`` SPIR-V operands opcode, size, alignment
- ``spirv.IntegralConstant`` integral type value
- ``spirv.Literal`` (none) value
- ========================== =================== ==============================
+ ========================== =================== =========================
+ LLVM type name LLVM type arguments LLVM integer arguments
+ ========================== =================== =========================
+ ``spirv.Type`` SPIR-V operands opcode, size, alignment
+ ``spirv.IntegralConstant`` integral type value
+ ``spirv.Literal`` (none) value
+ ========================== =================== =========================
The operand arguments to ``spirv.Type`` may be either a ``spirv.IntegralConstant`` type,
representing an ``OpConstant`` id operand, a ``spirv.Literal`` type, representing an immediate
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