[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilb (Long Branch) extension (PR #131996)

[Sam Elliott via llvm-commits]

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@@ -96,6 +96,21 @@ def simm32 : RISCVOp<XLenVT> {
   }];
 }
 
+// A 32-bit signed immediate where the least significant bit is zero.
+def simm32_lsb0 : Operand<OtherVT> {
+  let ParserMatchClass = SImmAsmOperand<32, "Lsb0">;
+  let PrintMethod = "printBranchOperand";
+  let EncoderMethod = "getImmOpValueAsr1";
+  let DecoderMethod = "decodeSImmOperandAndLsl1<32>";
+  let MCOperandPredicate = [{
+    int64_t Imm;
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isShiftedInt<31, 1>(Imm);
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lenary wrote:

Well that's a fun assembler difference I didn't know about :(

We've found it useful to write them for testing our assembler/disassembler, but agree that most users will use the symbol versions.

https://github.com/llvm/llvm-project/pull/131996