[llvm] [AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (PR #130933)

[Benjamin Maxwell via llvm-commits]

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@@ -1585,6 +1585,21 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::MSTORE, VT, Custom);
     }
 
+    for (MVT VT : MVT::integer_scalable_vector_valuetypes()) {
+      if (!EnablePartialReduceNodes)
+        break;
+      for (MVT InnerVT : MVT::integer_scalable_vector_valuetypes()) {
+        ElementCount VTElemCount = VT.getVectorElementCount();
+        if (VTElemCount.getKnownMinValue() == 1)
+          continue;
+        if (VTElemCount * 4 == InnerVT.getVectorElementCount())
+          setPartialReduceMLAAction(VT, InnerVT, Custom);
+        if (InnerVT.getVectorElementType().getSizeInBits() * 4 ==
+            VT.getVectorElementType().getSizeInBits())
+          setPartialReduceMLAAction(VT, InnerVT, Legal);
+      }
+    }
----------------
MacDue wrote:

I don't get this bit; this is going over all scalable int type pairs (which does not just include SVE legal types) and marking ones where the operand has 4x the elements as the accumulator as "Custom", and ones where the accumulator element type is 4x the operand element type as "Legal". 

But then looking at the ISEL lowering added in this patch ([AArch64SVEInstrInfo.td](https://github.com/llvm/llvm-project/pull/130933/files#diff-8c956339316422d3ff7117086727744d627fbfa1d0a265b55ddf5bbd8c46bfe6)) only  `(nxv4i32, nxv16i32)` and `(nxv2i64, nxvi8i16)` are legal combinations, and no type combinations have a custom lowering.

There's no `AArch64TargetLowering::LowerOperation` hook implemented for `ISD::PARTIAL_REDUCE_U/SMLA`, so if `LegalizeVectorOps` attempted a custom lowering we'd crash.

https://github.com/llvm/llvm-project/pull/130933