[llvm] [NVPTX] Improve 64bit FSH/ROT lowering when shift amount is constant (PR #131371)

[Justin Fargnoli via llvm-commits]

================
@@ -2758,6 +2764,53 @@ static SDValue lowerCTLZCTPOP(SDValue Op, SelectionDAG &DAG) {
   return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, CT, SDNodeFlags::NonNeg);
 }
 
+static SDValue expandFSH64(SDValue A, SDValue B, SDValue AmtVal, SDLoc DL,
+                           unsigned Opcode, SelectionDAG &DAG) {
+  assert(A.getValueType() == MVT::i64 && B.getValueType() == MVT::i64);
+
+  const auto *AmtConst = dyn_cast<ConstantSDNode>(AmtVal);
+  if (!AmtConst)
+    return SDValue();
+  const auto Amt = AmtConst->getZExtValue() & 63;
----------------
justinfargnoli wrote:

> The shift argument is treated as an unsigned amount modulo the element size of the arguments. ([source](https://llvm.org/docs/LangRef.html#llvm-fshl-intrinsic))

Interesting semantics. I would've guessed it's a bug to specify a number larger than the element size. 

https://github.com/llvm/llvm-project/pull/131371