[llvm] [RISCV] Xqciint SystemRegs, Final Assembly Insts (PR #130867)

[Sudharsan Veeravalli via llvm-commits]

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@@ -471,3 +471,34 @@ def : SysReg<"sctrstatus", 0x14f>;
 def : SysReg<"sctrdepth", 0x15f>;
 def : SysReg<"vsctrctl", 0x24e>;
 def : SysReg<"mctrctl", 0x34e>;
+
+//===-----------------------------------------------
+// Vendor CSRs
+//===-----------------------------------------------
+
+// Xqciint
+let FeaturesRequired = [{ {RISCV::FeatureVendorXqciint} }], isRV32Only = 1 in {
+def : SysReg<"qc.mmcr", 0x7C0>;
+def : SysReg<"qc.mnepc", 0x7C1>;
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svs-quic wrote:

The v0.7 spec removes these two.

>From the version history:

 Remove CSR registers qc.mncause, qc.mnep

https://github.com/llvm/llvm-project/pull/130867