[llvm] [NVPTX] Improve 64bit FSH/ROT lowering when shift amount is constant (PR #131371)

[Alex MacLean via llvm-commits]

================
@@ -445,6 +448,17 @@ bool NVPTXDAGToDAGISel::SelectSETP_BF16X2(SDNode *N) {
   return true;
 }
 
+bool NVPTXDAGToDAGISel::tryUNPACK_VECTOR(SDNode *N) {
+  SDValue Vector = N->getOperand(0);
+  MVT EltVT = N->getSimpleValueType(0);
+
+  MachineSDNode *N2 =
+      CurDAG->getMachineNode(NVPTX::I64toV2I32, SDLoc(N), EltVT, EltVT, Vector);
+
+  ReplaceNode(N, N2);
+  return true;
+}
+
----------------
AlexMaclean wrote:

I tried this but wasn't able to do it without llvm-tblgen crashing or hanging. I think table-gen support for nodes with multiple return values is not very reliable. 

https://github.com/llvm/llvm-project/pull/131371