[llvm] [RISCV] Update some of the RVV memory ops in SiFive P400 & P600 sched models (PR #129575)
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 17 11:19:04 PDT 2025
https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/129575
>From 43a5cbbb0cf7f4f2244dac25ba63e385e3125769 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Mon, 3 Mar 2025 11:11:19 -0800
Subject: [PATCH 1/3] [RISCV] Update some of the RVV memory ops in P400 & P600
sched models
---
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 99 ++-
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 99 ++-
.../llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s | 542 ++++++++++++++++
.../llvm-mca/RISCV/SiFiveP400/vlse-vsse.s | 316 ++++++++++
.../llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s | 588 +++++++++++++++++
.../llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s | 545 ++++++++++++++++
.../llvm-mca/RISCV/SiFiveP600/vlse-vsse.s | 319 ++++++++++
.../llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s | 591 ++++++++++++++++++
8 files changed, 2981 insertions(+), 118 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
index e7f8f88e3909f..00edb32d954c0 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
@@ -22,6 +22,8 @@ class SiFiveP400IsWorstCaseMXSEW<string mx, int sew, list<string> MxList, bit is
bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
}
+defvar SiFiveP400VLEN = 128;
+
// 1 Micro-Op per cycle.
class SiFiveP400GetLMulCycles<string mx> {
int c = !cond(
@@ -35,19 +37,19 @@ class SiFiveP400GetLMulCycles<string mx> {
);
}
-// Latency for segmented loads and stores are calculated as vl * nf.
-class SiFiveP400GetCyclesSegmented<string mx, int sew, int nf> {
- defvar VLEN = 128;
- defvar VLUpperBound = !cond(
- !eq(mx, "M1") : !div(VLEN, sew),
- !eq(mx, "M2") : !div(!mul(VLEN, 2), sew),
- !eq(mx, "M4") : !div(!mul(VLEN, 4), sew),
- !eq(mx, "M8") : !div(!mul(VLEN, 8), sew),
- !eq(mx, "MF2") : !div(!div(VLEN, 2), sew),
- !eq(mx, "MF4") : !div(!div(VLEN, 4), sew),
- !eq(mx, "MF8") : !div(!div(VLEN, 8), sew),
+class SiFiveP400GetVLMAX<string mx, int sew> {
+ defvar LMUL = SiFiveP400GetLMulCycles<mx>.c;
+ int val = !cond(
+ !eq(mx, "MF2") : !div(!div(SiFiveP400VLEN, 2), sew),
+ !eq(mx, "MF4") : !div(!div(SiFiveP400VLEN, 4), sew),
+ !eq(mx, "MF8") : !div(!div(SiFiveP400VLEN, 8), sew),
+ true: !div(!mul(SiFiveP400VLEN, LMUL), sew)
);
- int c = !mul(VLUpperBound, nf);
+}
+
+// Latency for segmented loads and stores are calculated as vl * nf.
+class SiFiveP400SegmentedLdStCycles<string mx, int sew, int nf> {
+ int c = !mul(SiFiveP400GetVLMAX<mx, sew>.val, nf);
}
// Both variants of floating point vector reductions are based on numbers collected
@@ -368,57 +370,36 @@ def : WriteRes<WriteVSETIVLI, [SiFiveP400SYS]>;
def : WriteRes<WriteVSETVL, [SiFiveP400SYS]>;
// 7. Vector Loads and Stores
-// FIXME: This unit is still being improved, currently
-// it is based on stage numbers. Estimates are optimistic,
-// latency may be longer.
-foreach mx = SchedMxList in {
- defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
- defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 8, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVLDE", [SiFiveP400VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP400VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDFF", [SiFiveP400VLD], mx, IsWorstCase>;
- }
- let Latency = 12, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVLDS8", [SiFiveP400VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDS16", [SiFiveP400VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDS32", [SiFiveP400VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDS64", [SiFiveP400VLD], mx, IsWorstCase>;
- }
- let Latency = 12, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVLDUX8", [SiFiveP400VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDUX16", [SiFiveP400VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDUX32", [SiFiveP400VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDUX64", [SiFiveP400VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDOX8", [SiFiveP400VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDOX16", [SiFiveP400VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDOX32", [SiFiveP400VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDOX64", [SiFiveP400VLD], mx, IsWorstCase>;
- }
-}
+// Note that the latency of vector loads are measured by consuming the loaded
+// value with vmv.x.s before subtracting the latency of vmv.x.s from the number.
foreach mx = SchedMxList in {
defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 8, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP400VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP400VST], mx, IsWorstCase>;
- }
- let Latency = 12, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVSTS8", [SiFiveP400VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTS16", [SiFiveP400VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTS32", [SiFiveP400VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTS64", [SiFiveP400VST], mx, IsWorstCase>;
+ let Latency = 8 in {
+ let ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVLDE", [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDFF", [SiFiveP400VLD], mx, IsWorstCase>;
+
+ defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP400VST], mx, IsWorstCase>;
+ }
+
+ // Mask load and store always have EMUL=1.
+ let ReleaseAtCycles = [SiFiveP400GetLMulCycles<"M1">.c] in {
+ defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP400VLD], mx, IsWorstCase=!eq(mx, "M1")>;
+ defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP400VST], mx, IsWorstCase=!eq(mx, "M1")>;
+ }
}
- let Latency = 12, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVSTUX8", [SiFiveP400VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTUX16", [SiFiveP400VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTUX32", [SiFiveP400VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTUX64", [SiFiveP400VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTOX8", [SiFiveP400VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTOX16", [SiFiveP400VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTOX32", [SiFiveP400VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTOX64", [SiFiveP400VST], mx, IsWorstCase>;
+ foreach eew = [8, 16, 32, 64] in {
+ let Latency = 13, ReleaseAtCycles = [SiFiveP400GetVLMAX<mx, eew>.val] in {
+ defm "" : LMULWriteResMX<"WriteVLDS" # eew, [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX" # eew, [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX" # eew, [SiFiveP400VLD], mx, IsWorstCase>;
+
+ defm "" : LMULWriteResMX<"WriteVSTS" # eew, [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX" # eew, [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX" # eew, [SiFiveP400VST], mx, IsWorstCase>;
+ }
}
}
@@ -426,7 +407,7 @@ foreach mx = SchedMxList in {
foreach nf=2-8 in {
foreach eew = [8, 16, 32, 64] in {
defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
- defvar LMulLat = SiFiveP400GetCyclesSegmented<mx, eew, nf>.c;
+ defvar LMulLat = SiFiveP400SegmentedLdStCycles<mx, eew, nf>.c;
let Latency = !add(12, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in {
defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" #eew, [SiFiveP400VLD], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" #eew, [SiFiveP400VLD], mx, IsWorstCase>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
index 60d41b02f0e8a..a66ca3dcd9790 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -22,6 +22,8 @@ class SiFiveP600IsWorstCaseMXSEW<string mx, int sew, list<string> MxList, bit is
bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
}
+defvar SiFiveP600VLEN = 128;
+
// 1 Micro-Op per cycle.
class SiFiveP600GetLMulCycles<string mx> {
int c = !cond(
@@ -35,19 +37,19 @@ class SiFiveP600GetLMulCycles<string mx> {
);
}
-// Latency for segmented loads and stores are calculated as vl * nf.
-class SiFiveP600GetCyclesSegmented<string mx, int sew, int nf> {
- defvar VLEN = 128;
- defvar VLUpperBound = !cond(
- !eq(mx, "M1") : !div(VLEN, sew),
- !eq(mx, "M2") : !div(!mul(VLEN, 2), sew),
- !eq(mx, "M4") : !div(!mul(VLEN, 4), sew),
- !eq(mx, "M8") : !div(!mul(VLEN, 8), sew),
- !eq(mx, "MF2") : !div(!div(VLEN, 2), sew),
- !eq(mx, "MF4") : !div(!div(VLEN, 4), sew),
- !eq(mx, "MF8") : !div(!div(VLEN, 8), sew),
+class SiFiveP600GetVLMAX<string mx, int sew> {
+ defvar LMUL = SiFiveP600GetLMulCycles<mx>.c;
+ int val = !cond(
+ !eq(mx, "MF2") : !div(!div(SiFiveP600VLEN, 2), sew),
+ !eq(mx, "MF4") : !div(!div(SiFiveP600VLEN, 4), sew),
+ !eq(mx, "MF8") : !div(!div(SiFiveP600VLEN, 8), sew),
+ true: !div(!mul(SiFiveP600VLEN, LMUL), sew)
);
- int c = !mul(VLUpperBound, nf);
+}
+
+// Latency for segmented loads and stores are calculated as vl * nf.
+class SiFiveP600SegmentedLdStCycles<string mx, int sew, int nf> {
+ int c = !mul(SiFiveP600GetVLMAX<mx, sew>.val, nf);
}
class SiFiveP600VSM3CCycles<string mx> {
@@ -544,64 +546,43 @@ def : WriteRes<WriteVSETIVLI, [SiFiveP600SYS]>;
def : WriteRes<WriteVSETVL, [SiFiveP600SYS]>;
// 7. Vector Loads and Stores
-// FIXME: This unit is still being improved, currently
-// it is based on stage numbers. Estimates are optimistic,
-// latency may be longer.
-foreach mx = SchedMxList in {
- defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
- defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 8, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVLDE", [SiFiveP600VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP600VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDFF", [SiFiveP600VLD], mx, IsWorstCase>;
- }
- let Latency = 12, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVLDS8", [SiFiveP600VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDS16", [SiFiveP600VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDS32", [SiFiveP600VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDS64", [SiFiveP600VLD], mx, IsWorstCase>;
- }
- let Latency = 12, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVLDUX8", [SiFiveP600VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDUX16", [SiFiveP600VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDUX32", [SiFiveP600VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDUX64", [SiFiveP600VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDOX8", [SiFiveP600VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDOX16", [SiFiveP600VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDOX32", [SiFiveP600VLD], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDOX64", [SiFiveP600VLD], mx, IsWorstCase>;
- }
-}
+// Note that the latency of vector loads are measured by consuming the loaded
+// value with vmv.x.s before subtracting the latency of vmv.x.s from the number.
foreach mx = SchedMxList in {
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 8, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP600VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP600VST], mx, IsWorstCase>;
- }
- let Latency = 12, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVSTS8", [SiFiveP600VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTS16", [SiFiveP600VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTS32", [SiFiveP600VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTS64", [SiFiveP600VST], mx, IsWorstCase>;
+ let Latency = 8 in {
+ let ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVLDE", [SiFiveP600VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDFF", [SiFiveP600VLD], mx, IsWorstCase>;
+
+ defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP600VST], mx, IsWorstCase>;
+ }
+
+ // Mask load and store always have EMUL=1.
+ let ReleaseAtCycles = [SiFiveP600GetLMulCycles<"M1">.c] in {
+ defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP600VLD], mx, IsWorstCase=!eq(mx,"M1")>;
+ defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP600VST], mx, IsWorstCase=!eq(mx,"M1")>;
+ }
}
- let Latency = 12, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVSTUX8", [SiFiveP600VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTUX16", [SiFiveP600VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTUX32", [SiFiveP600VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTUX64", [SiFiveP600VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTOX8", [SiFiveP600VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTOX16", [SiFiveP600VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTOX32", [SiFiveP600VST], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTOX64", [SiFiveP600VST], mx, IsWorstCase>;
+ foreach eew = [8, 16, 32, 64] in {
+ let Latency = 13, ReleaseAtCycles = [SiFiveP600GetVLMAX<mx, eew>.val] in {
+ defm "" : LMULWriteResMX<"WriteVLDS" # eew, [SiFiveP600VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX" # eew, [SiFiveP600VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX" # eew, [SiFiveP600VLD], mx, IsWorstCase>;
+
+ defm "" : LMULWriteResMX<"WriteVSTS" # eew, [SiFiveP600VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX" # eew, [SiFiveP600VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX" # eew, [SiFiveP600VST], mx, IsWorstCase>;
+ }
}
}
foreach mx = SchedMxList in {
foreach nf=2-8 in {
foreach eew = [8, 16, 32, 64] in {
- defvar LMulLat = SiFiveP600GetCyclesSegmented<mx, eew, nf>.c;
+ defvar LMulLat = SiFiveP600SegmentedLdStCycles<mx, eew, nf>.c;
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = !add(12, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in {
defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew, [SiFiveP600VLD], mx, IsWorstCase>;
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s
new file mode 100644
index 0000000000000..0f6802a17e0c5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vle-vse-vlm.s
@@ -0,0 +1,542 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, mf8, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vle8.v v8, (a0)
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, mf4, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vle16.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vle32.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vle64.v v8, (a0)
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, mf8, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vse8.v v8, (a0)
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, mf4, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vse16.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vse32.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vse64.v v8, (a0)
+
+# Unit-stride mask load/store
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, mf8, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vlm.v v8, (a0)
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, mf8, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vsm.v v8, (a0)
+
+# Fault-only-first
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, mf8, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vle8ff.v v8, (a0)
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, mf4, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vle16ff.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vle32ff.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vle64ff.v v8, (a0)
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 160
+# CHECK-NEXT: Total Cycles: 146
+# CHECK-NEXT: Total uOps: 160
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 1.10
+# CHECK-NEXT: IPC: 1.10
+# CHECK-NEXT: Block RThroughput: 139.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle64ff.v v8, (a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 80.00 - - - - - - 139.00 73.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vle64ff.v v8, (a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s
new file mode 100644
index 0000000000000..fe7fc577420cf
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s
@@ -0,0 +1,316 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf8, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vlse8.v v8, (a0), t0
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, mf4, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vlse16.v v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vlse32.v v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vlse64.v v8, (a0), t0
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf8, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vsse8.v v8, (a0), t0
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, mf4, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vsse16.v v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vsse32.v v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vsse64.v v8, (a0), t0
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 88
+# CHECK-NEXT: Total Cycles: 937
+# CHECK-NEXT: Total uOps: 88
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.09
+# CHECK-NEXT: IPC: 0.09
+# CHECK-NEXT: Block RThroughput: 472.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 13 128.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 13 128.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsse64.v v8, (a0), t0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 44.00 - - - - - - 472.00 472.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 64.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 128.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 64.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 128.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsse64.v v8, (a0), t0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s
new file mode 100644
index 0000000000000..6e71acc50a916
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s
@@ -0,0 +1,588 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf8, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vluxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf4, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vluxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vluxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vluxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf8, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vloxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf4, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vloxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vloxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vloxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf8, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vsuxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf4, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vsuxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vsuxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vsuxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf8, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vsoxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf4, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vsoxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vsoxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vsoxei64.v v8, (a0), v0
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 176
+# CHECK-NEXT: Total Cycles: 1881
+# CHECK-NEXT: Total uOps: 176
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.09
+# CHECK-NEXT: IPC: 0.09
+# CHECK-NEXT: Block RThroughput: 944.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 13 128.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 13 128.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 13 128.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 13 128.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsoxei64.v v8, (a0), v0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 88.00 - - - - - - 944.00 944.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 64.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 128.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 64.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 64.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 128.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 64.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 32.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 128.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 128.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 64.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 32.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - 16.00 vsoxei64.v v8, (a0), v0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s
new file mode 100644
index 0000000000000..3b62055e94463
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vle-vse-vlm.s
@@ -0,0 +1,545 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, mf8, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vle8.v v8, (a0)
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, mf4, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vle16.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vle32.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vle64.v v8, (a0)
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, mf8, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vse8.v v8, (a0)
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, mf4, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vse16.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vse32.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vse64.v v8, (a0)
+
+# Unit-stride mask load/store
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, mf8, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vlm.v v8, (a0)
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, mf8, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vsm.v v8, (a0)
+
+# Fault-only-first
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, mf8, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vle8ff.v v8, (a0)
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, mf4, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vle16ff.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vle32ff.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vle64ff.v v8, (a0)
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 160
+# CHECK-NEXT: Total Cycles: 146
+# CHECK-NEXT: Total uOps: 160
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 1.10
+# CHECK-NEXT: IPC: 1.10
+# CHECK-NEXT: Block RThroughput: 139.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * vle64ff.v v8, (a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 80.00 - - - - - - - - - 139.00 73.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vle64ff.v v8, (a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s
new file mode 100644
index 0000000000000..5bfe644e7c9e8
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s
@@ -0,0 +1,319 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf8, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vlse8.v v8, (a0), t0
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, mf4, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vlse16.v v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vlse32.v v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vlse64.v v8, (a0), t0
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf8, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vsse8.v v8, (a0), t0
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, mf4, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vsse16.v v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vsse32.v v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vsse64.v v8, (a0), t0
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 88
+# CHECK-NEXT: Total Cycles: 937
+# CHECK-NEXT: Total uOps: 88
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.09
+# CHECK-NEXT: IPC: 0.09
+# CHECK-NEXT: Block RThroughput: 472.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 13 128.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 13 128.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsse64.v v8, (a0), t0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 44.00 - - - - - - - - - 472.00 472.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 128.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 128.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsse64.v v8, (a0), t0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s
new file mode 100644
index 0000000000000..65afb2a5b7f77
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s
@@ -0,0 +1,591 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf8, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vluxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf4, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vluxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vluxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vluxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf8, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vloxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf4, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vloxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vloxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vloxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf8, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vsuxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf4, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vsuxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vsuxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vsuxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf8, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vsoxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf4, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vsoxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vsoxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vsoxei64.v v8, (a0), v0
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 176
+# CHECK-NEXT: Total Cycles: 1881
+# CHECK-NEXT: Total uOps: 176
+
+# CHECK: Dispatch Width: 4
+# CHECK-NEXT: uOps Per Cycle: 0.09
+# CHECK-NEXT: IPC: 0.09
+# CHECK-NEXT: Block RThroughput: 944.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 13 128.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 13 128.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 13 128.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 13 128.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 13 64.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 13 32.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 13 2.00 * vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 13 4.00 * vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 13 8.00 * vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 13 16.00 * vsoxei64.v v8, (a0), v0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP600Div
+# CHECK-NEXT: [1] - SiFiveP600FEXQ0
+# CHECK-NEXT: [2] - SiFiveP600FEXQ1
+# CHECK-NEXT: [3] - SiFiveP600FloatDiv
+# CHECK-NEXT: [4] - SiFiveP600IEXQ0
+# CHECK-NEXT: [5] - SiFiveP600IEXQ1
+# CHECK-NEXT: [6] - SiFiveP600IEXQ2
+# CHECK-NEXT: [7] - SiFiveP600IEXQ3
+# CHECK-NEXT: [8.0] - SiFiveP600LDST
+# CHECK-NEXT: [8.1] - SiFiveP600LDST
+# CHECK-NEXT: [9] - SiFiveP600VDiv
+# CHECK-NEXT: [10] - SiFiveP600VEXQ0
+# CHECK-NEXT: [11] - SiFiveP600VEXQ1
+# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
+# CHECK-NEXT: [13] - SiFiveP600VLD
+# CHECK-NEXT: [14] - SiFiveP600VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
+# CHECK-NEXT: - - - - 88.00 - - - - - - - - - 944.00 944.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 128.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 128.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 64.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 32.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 128.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 128.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 64.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 32.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - 16.00 vsoxei64.v v8, (a0), v0
>From fb424f79bf60c742bc9ece39442baad011e47eeb Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Mon, 17 Mar 2025 11:04:33 -0700
Subject: [PATCH 2/3] fixup! Update the latency of strided and indexed
loads/stores
---
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 15 +-
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 15 +-
.../llvm-mca/RISCV/SiFiveP400/vlse-vsse.s | 74 ++++-----
.../llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s | 146 +++++++++---------
.../llvm-mca/RISCV/SiFiveP600/vlse-vsse.s | 74 ++++-----
.../llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s | 146 +++++++++---------
6 files changed, 248 insertions(+), 222 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
index 00edb32d954c0..054c0c684dab8 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
@@ -47,6 +47,18 @@ class SiFiveP400GetVLMAX<string mx, int sew> {
);
}
+class SiFiveP400StridedLdStLatency<string mx, int sew> {
+ defvar VL = SiFiveP400GetVLMAX<mx, sew>.val;
+ int val = !cond(
+ !eq(VL, 2): 13,
+ !eq(VL, 4): 18,
+ !eq(VL, 8): 22,
+ !eq(VL, 16): 30,
+ // VL=32,64,128
+ true: !sub(VL, 2)
+ );
+}
+
// Latency for segmented loads and stores are calculated as vl * nf.
class SiFiveP400SegmentedLdStCycles<string mx, int sew, int nf> {
int c = !mul(SiFiveP400GetVLMAX<mx, sew>.val, nf);
@@ -391,7 +403,8 @@ foreach mx = SchedMxList in {
}
}
foreach eew = [8, 16, 32, 64] in {
- let Latency = 13, ReleaseAtCycles = [SiFiveP400GetVLMAX<mx, eew>.val] in {
+ let Latency = SiFiveP400StridedLdStLatency<mx, eew>.val,
+ ReleaseAtCycles = [SiFiveP400GetVLMAX<mx, eew>.val] in {
defm "" : LMULWriteResMX<"WriteVLDS" # eew, [SiFiveP400VLD], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDUX" # eew, [SiFiveP400VLD], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDOX" # eew, [SiFiveP400VLD], mx, IsWorstCase>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
index a66ca3dcd9790..86e2c44907746 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -47,6 +47,18 @@ class SiFiveP600GetVLMAX<string mx, int sew> {
);
}
+class SiFiveP600StridedLdStLatency<string mx, int sew> {
+ defvar VL = SiFiveP400GetVLMAX<mx, sew>.val;
+ int val = !cond(
+ !eq(VL, 2): 13,
+ !eq(VL, 4): 18,
+ !eq(VL, 8): 22,
+ !eq(VL, 16): 30,
+ // VL=32,64,128
+ true: !sub(VL, 2)
+ );
+}
+
// Latency for segmented loads and stores are calculated as vl * nf.
class SiFiveP600SegmentedLdStCycles<string mx, int sew, int nf> {
int c = !mul(SiFiveP600GetVLMAX<mx, sew>.val, nf);
@@ -567,7 +579,8 @@ foreach mx = SchedMxList in {
}
}
foreach eew = [8, 16, 32, 64] in {
- let Latency = 13, ReleaseAtCycles = [SiFiveP600GetVLMAX<mx, eew>.val] in {
+ let Latency = SiFiveP600StridedLdStLatency<mx, eew>.val,
+ ReleaseAtCycles = [SiFiveP600GetVLMAX<mx, eew>.val] in {
defm "" : LMULWriteResMX<"WriteVLDS" # eew, [SiFiveP600VLD], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDUX" # eew, [SiFiveP600VLD], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDOX" # eew, [SiFiveP600VLD], mx, IsWorstCase>;
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s
index fe7fc577420cf..15e2b96a62ca7 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlse-vsse.s
@@ -99,7 +99,7 @@ vsse64.v v8, (a0), t0
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 88
-# CHECK-NEXT: Total Cycles: 937
+# CHECK-NEXT: Total Cycles: 954
# CHECK-NEXT: Total uOps: 88
# CHECK: Dispatch Width: 3
@@ -117,93 +117,93 @@ vsse64.v v8, (a0), t0
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vlse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vlse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
# CHECK-NEXT: 1 13 2.00 * vlse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vlse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 30 32.00 * vlse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 62 64.00 * vlse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 13 128.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 126 128.00 * vlse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vlse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
# CHECK-NEXT: 1 13 2.00 * vlse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vlse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vlse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 30 32.00 * vlse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 62 64.00 * vlse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
# CHECK-NEXT: 1 13 2.00 * vlse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vlse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vlse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vlse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 30 32.00 * vlse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
# CHECK-NEXT: 1 13 2.00 * vlse64.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vlse64.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vlse64.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vlse64.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vsse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vsse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vsse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 30 32.00 * vsse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 62 64.00 * vsse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 13 128.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 126 128.00 * vsse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vsse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vsse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vsse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 30 32.00 * vsse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 62 64.00 * vsse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vsse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vsse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vsse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 30 32.00 * vsse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsse64.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vsse64.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vsse64.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vsse64.v v8, (a0), t0
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFiveP400Div
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s
index 6e71acc50a916..203594ea89424 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlxe-vsxe.s
@@ -195,7 +195,7 @@ vsoxei64.v v8, (a0), v0
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 176
-# CHECK-NEXT: Total Cycles: 1881
+# CHECK-NEXT: Total Cycles: 1898
# CHECK-NEXT: Total uOps: 176
# CHECK: Dispatch Width: 3
@@ -213,181 +213,181 @@ vsoxei64.v v8, (a0), v0
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vluxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vluxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
# CHECK-NEXT: 1 13 2.00 * vluxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vluxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vluxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vluxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 13 128.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 126 128.00 * vluxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vluxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
# CHECK-NEXT: 1 13 2.00 * vluxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vluxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vluxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vluxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vluxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
# CHECK-NEXT: 1 13 2.00 * vluxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vluxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vluxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vluxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vluxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
# CHECK-NEXT: 1 13 2.00 * vluxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vluxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vluxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vluxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vloxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vloxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
# CHECK-NEXT: 1 13 2.00 * vloxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vloxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vloxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vloxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 13 128.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 126 128.00 * vloxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vloxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
# CHECK-NEXT: 1 13 2.00 * vloxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vloxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vloxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vloxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vloxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
# CHECK-NEXT: 1 13 2.00 * vloxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vloxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vloxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vloxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vloxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
# CHECK-NEXT: 1 13 2.00 * vloxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vloxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vloxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vloxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsuxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsuxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsuxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsuxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vsuxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vsuxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 13 128.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 126 128.00 * vsuxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsuxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsuxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsuxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsuxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vsuxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vsuxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsuxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsuxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsuxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsuxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vsuxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsuxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsuxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsuxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsuxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsoxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsoxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsoxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsoxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vsoxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vsoxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 13 128.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 126 128.00 * vsoxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsoxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsoxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsoxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsoxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vsoxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vsoxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsoxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsoxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsoxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsoxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vsoxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsoxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsoxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsoxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsoxei64.v v8, (a0), v0
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFiveP400Div
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s
index 5bfe644e7c9e8..7363755828134 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlse-vsse.s
@@ -99,7 +99,7 @@ vsse64.v v8, (a0), t0
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 88
-# CHECK-NEXT: Total Cycles: 937
+# CHECK-NEXT: Total Cycles: 954
# CHECK-NEXT: Total uOps: 88
# CHECK: Dispatch Width: 4
@@ -117,93 +117,93 @@ vsse64.v v8, (a0), t0
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vlse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vlse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
# CHECK-NEXT: 1 13 2.00 * vlse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vlse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 30 32.00 * vlse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 62 64.00 * vlse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 13 128.00 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 126 128.00 * vlse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vlse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
# CHECK-NEXT: 1 13 2.00 * vlse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vlse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vlse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 30 32.00 * vlse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 62 64.00 * vlse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
# CHECK-NEXT: 1 13 2.00 * vlse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vlse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vlse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vlse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 30 32.00 * vlse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
# CHECK-NEXT: 1 13 2.00 * vlse64.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vlse64.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vlse64.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vlse64.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vsse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vsse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vsse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 30 32.00 * vsse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 62 64.00 * vsse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 13 128.00 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 126 128.00 * vsse8.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vsse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vsse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vsse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 30 32.00 * vsse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 62 64.00 * vsse16.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vsse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vsse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vsse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 30 32.00 * vsse32.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsse64.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 18 4.00 * vsse64.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 22 8.00 * vsse64.v v8, (a0), t0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 30 16.00 * vsse64.v v8, (a0), t0
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFiveP600Div
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s
index 65afb2a5b7f77..851c241505e53 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP600/vlxe-vsxe.s
@@ -195,7 +195,7 @@ vsoxei64.v v8, (a0), v0
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 176
-# CHECK-NEXT: Total Cycles: 1881
+# CHECK-NEXT: Total Cycles: 1898
# CHECK-NEXT: Total uOps: 176
# CHECK: Dispatch Width: 4
@@ -213,181 +213,181 @@ vsoxei64.v v8, (a0), v0
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vluxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vluxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
# CHECK-NEXT: 1 13 2.00 * vluxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vluxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vluxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vluxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 13 128.00 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 126 128.00 * vluxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vluxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
# CHECK-NEXT: 1 13 2.00 * vluxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vluxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vluxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vluxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vluxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
# CHECK-NEXT: 1 13 2.00 * vluxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vluxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vluxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vluxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vluxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
# CHECK-NEXT: 1 13 2.00 * vluxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vluxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vluxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vluxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vloxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vloxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
# CHECK-NEXT: 1 13 2.00 * vloxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vloxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vloxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vloxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 13 128.00 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 126 128.00 * vloxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vloxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
# CHECK-NEXT: 1 13 2.00 * vloxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vloxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vloxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vloxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vloxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
# CHECK-NEXT: 1 13 2.00 * vloxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vloxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vloxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vloxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vloxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
# CHECK-NEXT: 1 13 2.00 * vloxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vloxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vloxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vloxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsuxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsuxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsuxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsuxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vsuxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vsuxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 13 128.00 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 126 128.00 * vsuxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsuxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsuxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsuxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsuxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vsuxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vsuxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsuxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsuxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsuxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsuxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vsuxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsuxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsuxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsuxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsuxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsoxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsoxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsoxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsoxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vsoxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vsoxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 13 128.00 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 126 128.00 * vsoxei8.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsoxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsoxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsoxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsoxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vsoxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 13 64.00 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 62 64.00 * vsoxei16.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsoxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsoxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsoxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsoxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 13 32.00 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 30 32.00 * vsoxei32.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, ta, ma
# CHECK-NEXT: 1 13 2.00 * vsoxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 13 4.00 * vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 18 4.00 * vsoxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 13 8.00 * vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 22 8.00 * vsoxei64.v v8, (a0), v0
# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 13 16.00 * vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 30 16.00 * vsoxei64.v v8, (a0), v0
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFiveP600Div
>From ad8229b9d2c7e61d62f2098f6431a7718b6b1463 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Mon, 17 Mar 2025 11:18:34 -0700
Subject: [PATCH 3/3] fixup! Update comment about EMUL of mask-producing
instructions
---
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 2 +-
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
index 054c0c684dab8..1ac05c9444725 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
@@ -396,7 +396,7 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP400VST], mx, IsWorstCase>;
}
- // Mask load and store always have EMUL=1.
+ // Mask load and store have a maximum EMUL of 1.
let ReleaseAtCycles = [SiFiveP400GetLMulCycles<"M1">.c] in {
defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP400VLD], mx, IsWorstCase=!eq(mx, "M1")>;
defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP400VST], mx, IsWorstCase=!eq(mx, "M1")>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
index 86e2c44907746..2bfd5ef811c7b 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -572,7 +572,7 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP600VST], mx, IsWorstCase>;
}
- // Mask load and store always have EMUL=1.
+ // Mask load and store have a maximum EMUL of 1.
let ReleaseAtCycles = [SiFiveP600GetLMulCycles<"M1">.c] in {
defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP600VLD], mx, IsWorstCase=!eq(mx,"M1")>;
defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP600VST], mx, IsWorstCase=!eq(mx,"M1")>;
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