[llvm] [RISCV] Add DAG combine for (vmv_s_x_vl merge, (and scalar, mask), vl). (PR #131711)

[Craig Topper via llvm-commits]

topperc wrote:

> > We should call SimplifyDemandedBits on the vmv_s_x_vl input rather than checking specifically for ISD::AND.
> > Similar code is here where `SimplifyDemandedBits` is wrapped by `SimplifyDemandedLowBitsHelper`
> > ```
> >   case RISCVISD::VMV_V_X_VL: {
> >     const MVT VT = N->getSimpleValueType(0);
> >     SDValue Passthru = N->getOperand(0);
> >     SDValue Scalar = N->getOperand(1);
> >     SDValue VL = N->getOperand(2);
> > 
> >     // Tail agnostic VMV.V.X only demands the vector element bitwidth from the
> >     // scalar input.
> >     unsigned ScalarSize = Scalar.getValueSizeInBits();
> >     unsigned EltWidth = VT.getScalarSizeInBits();
> >     if (ScalarSize > EltWidth && Passthru.isUndef())
> >       if (SimplifyDemandedLowBitsHelper(1, EltWidth))
> >         return SDValue(N, 0);
> > ```
> 
> Do we need to care whether the merge operand is undef?

I don't think so. I don't know why that's in there.

https://github.com/llvm/llvm-project/pull/131711