[llvm] RISCV: Implement isLoadFromStackSlot/isStoreToStackSlot for rvv (PR #120524)

[Philip Reames via llvm-commits]

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@@ -118,6 +118,12 @@ Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
   case RISCV::FLD:
     MemBytes = 8;
     break;
+  case RISCV::VL8RE8_V:
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preames wrote:

FYI, this includes all of the instructions we actually use for reloading vector registers from the stack.  There are other instructions we could use, but not that we *do* use.  (Excluding the segment spill stuff as it's own sub-problem.)

https://github.com/llvm/llvm-project/pull/120524