[llvm] [RISCV] Add DAG combine for (vmv_s_x_vl merge, (and scalar, mask), vl). (PR #131711)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 17 20:46:56 PDT 2025

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topperc wrote:

We should call SimplifyDemandedBits on the vmv_s_x_vl input rather than checking specifically for ISD::AND.

https://github.com/llvm/llvm-project/pull/131711

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