[llvm] [SelectionDAG][RISCV] Avoid store merging across function calls (PR #130430)

[Philip Reames via llvm-commits]

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@@ -1,7 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
 
-declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
 declare void @g()
 
 ; TODO: Merging scalars into vectors is unprofitable because we have no
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preames wrote:

Remember to update the TODO

https://github.com/llvm/llvm-project/pull/130430