[llvm] [RISCV] Xqciint SystemRegs, Final Assembly Insts (PR #130867)
Sam Elliott via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 18 10:33:30 PDT 2025
https://github.com/lenary updated https://github.com/llvm/llvm-project/pull/130867
>From ee928c0de65e097c98b0433e147caa06143ee42b Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Tue, 11 Mar 2025 17:12:02 -0700
Subject: [PATCH 1/2] [RISCV] Xqciint SystemRegs, Final Assembly Insts
This adds the Xqciint system registers from the Xqci-0.7 spec, as well
as two leftover instructions: `qc.c.mret` and `qc.c.mnret`
Co-authored-by: Sudharsan Veeravalli <quic_svs at quicinc.com>
---
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 59 +--
llvm/lib/Target/RISCV/RISCVSystemOperands.td | 31 ++
llvm/test/MC/RISCV/xqciint-csrs-invalid.s | 196 ++++++++
llvm/test/MC/RISCV/xqciint-csrs-valid.s | 454 +++++++++++++++++++
llvm/test/MC/RISCV/xqciint-invalid.s | 14 +
llvm/test/MC/RISCV/xqciint-valid.s | 10 +
6 files changed, 738 insertions(+), 26 deletions(-)
create mode 100644 llvm/test/MC/RISCV/xqciint-csrs-invalid.s
create mode 100644 llvm/test/MC/RISCV/xqciint-csrs-valid.s
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 32cfade8697b9..d639859206d0e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -545,38 +545,45 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
} // Predicates = [HasVendorXqcicm, IsRV32]
let Predicates = [HasVendorXqciint, IsRV32], hasSideEffects = 1 in {
- let mayLoad = 0, mayStore = 0 in {
- def QC_C_DIR : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd), (ins),
- "qc.c.dir", "$rd"> {
- bits<5> rd;
- let Inst{12} = 0b1;
- let Inst{11-7} = rd;
- let Inst{6-2} = 0b00000;
- }
+let mayLoad = 0, mayStore = 0 in {
+def QC_C_DIR : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd), (ins),
+ "qc.c.dir", "$rd"> {
+ bits<5> rd;
+
+ let Inst{12} = 0b1;
+ let Inst{11-7} = rd;
+ let Inst{6-2} = 0b00000;
+}
+
+def QC_SETINTI : QCIInt_IMM<0b0, "qc.setinti">;
+def QC_CLRINTI : QCIInt_IMM<0b1, "qc.clrinti">;
+
+def QC_C_EIR : QCIRVInst16CI_RS1<0b00001, "qc.c.eir">;
+def QC_C_SETINT : QCIRVInst16CI_RS1<0b00010, "qc.c.setint">;
+def QC_C_CLRINT : QCIRVInst16CI_RS1<0b00011, "qc.c.clrint">;
- def QC_SETINTI : QCIInt_IMM<0b0, "qc.setinti">;
- def QC_CLRINTI : QCIInt_IMM<0b1, "qc.clrinti">;
+def QC_C_DI : QCIRVInst16CI_NONE<0b10110, "qc.c.di">;
+def QC_C_EI : QCIRVInst16CI_NONE<0b10111, "qc.c.ei">;
- def QC_C_EIR : QCIRVInst16CI_RS1<0b00001, "qc.c.eir">;
- def QC_C_SETINT : QCIRVInst16CI_RS1<0b00010, "qc.c.setint">;
- def QC_C_CLRINT : QCIRVInst16CI_RS1<0b00011, "qc.c.clrint">;
+let isBarrier = 1, isReturn = 1, isTerminator = 1 in {
+def QC_C_MRET : QCIRVInst16CI_NONE<0b10010, "qc.c.mret">;
+def QC_C_MNRET : QCIRVInst16CI_NONE<0b10011, "qc.c.mnret">;
+} // isBarrier = 1, isReturn = 1, isTerminator = 1
+} // mayLoad = 0, mayStore = 0
- def QC_C_DI : QCIRVInst16CI_NONE<0b10110, "qc.c.di">;
- def QC_C_EI : QCIRVInst16CI_NONE<0b10111, "qc.c.ei">;
- } // mayLoad = 0, mayStore = 0
+let mayLoad = 0, mayStore = 1,
+ Uses = [X1, X2, X5, X6, X7, X8, X10, X11, X12, X13, X14, X15, X16, X17, X28, X29, X30, X31],
+ Defs = [X2, X8] in {
+def QC_C_MIENTER : QCIRVInst16CI_NONE<0b10000, "qc.c.mienter">;
+def QC_C_MIENTER_NEST : QCIRVInst16CI_NONE<0b10001, "qc.c.mienter.nest">;
+} // mayLoad = 1, mayStore = 1, Uses = [...], Defs = [...]
- let mayLoad = 0, mayStore = 1,
- Uses = [X1, X2, X5, X6, X7, X8, X10, X11, X12, X13, X14, X15, X16, X17, X28, X29, X30, X31],
- Defs = [X2, X8] in {
- def QC_C_MIENTER : QCIRVInst16CI_NONE<0b10000, "qc.c.mienter">;
- def QC_C_MIENTER_NEST : QCIRVInst16CI_NONE<0b10001, "qc.c.mienter.nest">;
- } // mayLoad = 1, mayStore = 1, Uses = [...], Defs = [...]
+let mayLoad = 1, mayStore = 0, isBarrier = 1, isReturn = 1, isTerminator = 1,
+ Uses = [X2],
+ Defs = [X1, X2, X5, X6, X7, X8, X10, X11, X12, X13, X14, X15, X16, X17, X28, X29, X30, X31] in
+def QC_C_MILEAVERET : QCIRVInst16CI_NONE<0b10100, "qc.c.mileaveret">;
- let mayLoad = 1, mayStore = 0, isBarrier = 1, isReturn = 1, isTerminator = 1,
- Uses = [X2],
- Defs = [X1, X2, X5, X6, X7, X8, X10, X11, X12, X13, X14, X15, X16, X17, X28, X29, X30, X31] in
- def QC_C_MILEAVERET : QCIRVInst16CI_NONE<0b10100, "qc.c.mileaveret">;
} // Predicates = [HasVendorXqciint, IsRV32], hasSideEffects = 1
let Predicates = [HasVendorXqcilo, IsRV32] in {
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 5b46e7df25fc8..4c7db896e3380 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -471,3 +471,34 @@ def : SysReg<"sctrstatus", 0x14f>;
def : SysReg<"sctrdepth", 0x15f>;
def : SysReg<"vsctrctl", 0x24e>;
def : SysReg<"mctrctl", 0x34e>;
+
+//===-----------------------------------------------
+// Vendor CSRs
+//===-----------------------------------------------
+
+// Xqciint
+let FeaturesRequired = [{ {RISCV::FeatureVendorXqciint} }], isRV32Only = 1 in {
+def : SysReg<"qc.mmcr", 0x7C0>;
+def : SysReg<"qc.mnepc", 0x7C1>;
+def : SysReg<"qc.mncause", 0x7C2>;
+def : SysReg<"qc.mntvec", 0x7C3>;
+def : SysReg<"qc.mstktopaddr", 0x7C4>;
+def : SysReg<"qc.mstkbottomaddr", 0x7C5>;
+def : SysReg<"qc.mthreadptr", 0x7C8>;
+def : SysReg<"qc.mcause", 0x7C9>;
+
+foreach i = 0 - 7 in {
+ def : SysReg<"qc.mclicip" # i, !add(0x7F0, i)>;
+ def : SysReg<"qc.mclicie" # i, !add(0x7F8, i)>;
+}
+
+foreach i = 0 - 31 in {
+ def : SysReg<"qc.mclicilvl" # !if(!lt(i, 10), "0", "") # i,
+ !add(0xBC0, i)>;
+}
+
+foreach i = 0 - 3 in {
+ def : SysReg<"qc.mwpstartaddr" # i, !add(0x7D0, i)>;
+ def : SysReg<"qc.mwpendaddr" # i, !add(0x7D4, i)>;
+}
+} // FeatureVendorXqciint, isRV32Only
diff --git a/llvm/test/MC/RISCV/xqciint-csrs-invalid.s b/llvm/test/MC/RISCV/xqciint-csrs-invalid.s
new file mode 100644
index 0000000000000..02244e65194e1
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqciint-csrs-invalid.s
@@ -0,0 +1,196 @@
+# Xqciint - Qualcomm uC Custom CSRs
+# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqciint < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-FEATURE %s
+
+csrrs t2, qc.mmcr, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mmcr' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mnepc, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mnepc' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mncause, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mncause' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mntvec, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mntvec' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mstktopaddr, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mstktopaddr' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mstkbottomaddr, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mstkbottomaddr' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mthreadptr, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mthreadptr' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mcause, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mcause' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip0, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip0' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip1, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip1' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip2, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip2' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip3, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip3' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip4, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip4' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip5, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip5' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip6, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip6' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicip7, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip7' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie0, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie0' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie1, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie1' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie2, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie2' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie3, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie3' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie4, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie4' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie5, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie5' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie6, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie6' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicie7, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie7' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl00, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl00' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl01, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl01' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl02, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl02' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl03, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl03' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl04, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl04' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl05, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl05' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl06, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl06' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl07, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl07' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl08, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl08' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl09, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl09' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl10, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl10' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl11, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl11' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl12, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl12' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl13, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl13' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl14, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl14' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl15, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl15' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl16, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl16' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl17, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl17' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl18, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl18' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl19, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl19' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl20, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl20' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl21, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl21' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl22, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl22' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl23, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl23' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl24, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl24' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl25, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl25' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl26, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl26' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl27, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl27' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl28, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl28' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl29, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl29' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl30, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl30' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mclicilvl31, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl31' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpstartaddr0, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr0' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpstartaddr1, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr1' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpstartaddr2, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr2' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpstartaddr3, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr3' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpendaddr0, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr0' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpendaddr1, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr1' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpendaddr2, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr2' requires 'experimental-xqciint' to be enabled
+
+csrrs t2, qc.mwpendaddr3, zero
+// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr3' requires 'experimental-xqciint' to be enabled
+
diff --git a/llvm/test/MC/RISCV/xqciint-csrs-valid.s b/llvm/test/MC/RISCV/xqciint-csrs-valid.s
new file mode 100644
index 0000000000000..ed6ac13d8a7a7
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqciint-csrs-valid.s
@@ -0,0 +1,454 @@
+# Xqciint - Qualcomm uC Custom CSRs
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciint -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciint < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xqciint -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+csrrs t2, qc.mmcr, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7c]
+// CHECK-INST: csrrs t2, qc.mmcr, zero
+csrrs t2, 0x7C0, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7c]
+// CHECK-INST: csrrs t2, qc.mmcr, zero
+
+csrrs t2, qc.mnepc, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c]
+// CHECK-INST: csrrs t2, qc.mnepc, zero
+csrrs t2, 0x7C1, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c]
+// CHECK-INST: csrrs t2, qc.mnepc, zero
+
+csrrs t2, qc.mncause, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7c]
+// CHECK-INST: csrrs t2, qc.mncause, zero
+csrrs t2, 0x7C2, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7c]
+// CHECK-INST: csrrs t2, qc.mncause, zero
+
+csrrs t2, qc.mntvec, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7c]
+// CHECK-INST: csrrs t2, qc.mntvec, zero
+csrrs t2, 0x7C3, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7c]
+// CHECK-INST: csrrs t2, qc.mntvec, zero
+
+csrrs t2, qc.mstktopaddr, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x40,0x7c]
+// CHECK-INST: csrrs t2, qc.mstktopaddr, zero
+csrrs t2, 0x7C4, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x40,0x7c]
+// CHECK-INST: csrrs t2, qc.mstktopaddr, zero
+
+csrrs t2, qc.mstkbottomaddr, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x50,0x7c]
+// CHECK-INST: csrrs t2, qc.mstkbottomaddr, zero
+csrrs t2, 0x7C5, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x50,0x7c]
+// CHECK-INST: csrrs t2, qc.mstkbottomaddr, zero
+
+csrrs t2, qc.mthreadptr, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7c]
+// CHECK-INST: csrrs t2, qc.mthreadptr, zero
+csrrs t2, 0x7C8, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7c]
+// CHECK-INST: csrrs t2, qc.mthreadptr, zero
+
+csrrs t2, qc.mcause, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x90,0x7c]
+// CHECK-INST: csrrs t2, qc.mcause, zero
+csrrs t2, 0x7C9, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x90,0x7c]
+// CHECK-INST: csrrs t2, qc.mcause, zero
+
+csrrs t2, qc.mclicip0, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip0, zero
+csrrs t2, 0x7F0, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip0, zero
+
+csrrs t2, qc.mclicip1, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip1, zero
+csrrs t2, 0x7F1, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip1, zero
+
+csrrs t2, qc.mclicip2, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip2, zero
+csrrs t2, 0x7F2, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip2, zero
+
+csrrs t2, qc.mclicip3, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip3, zero
+csrrs t2, 0x7F3, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip3, zero
+
+csrrs t2, qc.mclicip4, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x40,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip4, zero
+csrrs t2, 0x7F4, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x40,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip4, zero
+
+csrrs t2, qc.mclicip5, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x50,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip5, zero
+csrrs t2, 0x7F5, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x50,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip5, zero
+
+csrrs t2, qc.mclicip6, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x60,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip6, zero
+csrrs t2, 0x7F6, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x60,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip6, zero
+
+csrrs t2, qc.mclicip7, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x70,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip7, zero
+csrrs t2, 0x7F7, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x70,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicip7, zero
+
+csrrs t2, qc.mclicie0, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie0, zero
+csrrs t2, 0x7F8, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie0, zero
+
+csrrs t2, qc.mclicie1, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x90,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie1, zero
+csrrs t2, 0x7F9, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x90,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie1, zero
+
+csrrs t2, qc.mclicie2, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie2, zero
+csrrs t2, 0x7FA, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie2, zero
+
+csrrs t2, qc.mclicie3, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xb0,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie3, zero
+csrrs t2, 0x7FB, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xb0,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie3, zero
+
+csrrs t2, qc.mclicie4, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie4, zero
+csrrs t2, 0x7FC, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie4, zero
+
+csrrs t2, qc.mclicie5, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie5, zero
+csrrs t2, 0x7FD, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie5, zero
+
+csrrs t2, qc.mclicie6, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie6, zero
+csrrs t2, 0x7FE, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie6, zero
+
+csrrs t2, qc.mclicie7, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie7, zero
+csrrs t2, 0x7FF, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x7f]
+// CHECK-INST: csrrs t2, qc.mclicie7, zero
+
+csrrs t2, qc.mclicilvl00, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x00,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl00, zero
+csrrs t2, 0xBC0, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x00,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl00, zero
+
+csrrs t2, qc.mclicilvl01, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x10,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl01, zero
+csrrs t2, 0xBC1, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x10,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl01, zero
+
+csrrs t2, qc.mclicilvl02, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x20,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl02, zero
+csrrs t2, 0xBC2, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x20,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl02, zero
+
+csrrs t2, qc.mclicilvl03, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x30,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl03, zero
+csrrs t2, 0xBC3, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x30,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl03, zero
+
+csrrs t2, qc.mclicilvl04, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x40,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl04, zero
+csrrs t2, 0xBC4, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x40,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl04, zero
+
+csrrs t2, qc.mclicilvl05, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x50,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl05, zero
+csrrs t2, 0xBC5, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x50,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl05, zero
+
+csrrs t2, qc.mclicilvl06, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x60,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl06, zero
+csrrs t2, 0xBC6, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x60,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl06, zero
+
+csrrs t2, qc.mclicilvl07, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x70,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl07, zero
+csrrs t2, 0xBC7, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x70,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl07, zero
+
+csrrs t2, qc.mclicilvl08, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x80,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl08, zero
+csrrs t2, 0xBC8, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x80,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl08, zero
+
+csrrs t2, qc.mclicilvl09, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x90,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl09, zero
+csrrs t2, 0xBC9, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x90,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl09, zero
+
+csrrs t2, qc.mclicilvl10, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xa0,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl10, zero
+csrrs t2, 0xBCA, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xa0,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl10, zero
+
+csrrs t2, qc.mclicilvl11, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xb0,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl11, zero
+csrrs t2, 0xBCB, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xb0,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl11, zero
+
+csrrs t2, qc.mclicilvl12, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xc0,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl12, zero
+csrrs t2, 0xBCC, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xc0,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl12, zero
+
+csrrs t2, qc.mclicilvl13, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xd0,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl13, zero
+csrrs t2, 0xBCD, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xd0,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl13, zero
+
+csrrs t2, qc.mclicilvl14, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xe0,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl14, zero
+csrrs t2, 0xBCE, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xe0,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl14, zero
+
+csrrs t2, qc.mclicilvl15, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xf0,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl15, zero
+csrrs t2, 0xBCF, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xf0,0xbc]
+// CHECK-INST: csrrs t2, qc.mclicilvl15, zero
+
+csrrs t2, qc.mclicilvl16, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x00,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl16, zero
+csrrs t2, 0xBD0, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x00,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl16, zero
+
+csrrs t2, qc.mclicilvl17, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x10,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl17, zero
+csrrs t2, 0xBD1, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x10,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl17, zero
+
+csrrs t2, qc.mclicilvl18, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x20,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl18, zero
+csrrs t2, 0xBD2, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x20,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl18, zero
+
+csrrs t2, qc.mclicilvl19, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x30,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl19, zero
+csrrs t2, 0xBD3, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x30,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl19, zero
+
+csrrs t2, qc.mclicilvl20, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x40,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl20, zero
+csrrs t2, 0xBD4, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x40,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl20, zero
+
+csrrs t2, qc.mclicilvl21, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x50,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl21, zero
+csrrs t2, 0xBD5, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x50,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl21, zero
+
+csrrs t2, qc.mclicilvl22, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x60,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl22, zero
+csrrs t2, 0xBD6, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x60,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl22, zero
+
+csrrs t2, qc.mclicilvl23, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x70,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl23, zero
+csrrs t2, 0xBD7, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x70,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl23, zero
+
+csrrs t2, qc.mclicilvl24, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x80,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl24, zero
+csrrs t2, 0xBD8, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x80,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl24, zero
+
+csrrs t2, qc.mclicilvl25, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x90,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl25, zero
+csrrs t2, 0xBD9, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x90,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl25, zero
+
+csrrs t2, qc.mclicilvl26, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xa0,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl26, zero
+csrrs t2, 0xBDA, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xa0,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl26, zero
+
+csrrs t2, qc.mclicilvl27, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xb0,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl27, zero
+csrrs t2, 0xBDB, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xb0,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl27, zero
+
+csrrs t2, qc.mclicilvl28, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xc0,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl28, zero
+csrrs t2, 0xBDC, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xc0,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl28, zero
+
+csrrs t2, qc.mclicilvl29, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xd0,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl29, zero
+csrrs t2, 0xBDD, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xd0,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl29, zero
+
+csrrs t2, qc.mclicilvl30, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xe0,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl30, zero
+csrrs t2, 0xBDE, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xe0,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl30, zero
+
+csrrs t2, qc.mclicilvl31, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xf0,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl31, zero
+csrrs t2, 0xBDF, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0xf0,0xbd]
+// CHECK-INST: csrrs t2, qc.mclicilvl31, zero
+
+csrrs t2, qc.mwpstartaddr0, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpstartaddr0, zero
+csrrs t2, 0x7D0, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpstartaddr0, zero
+
+csrrs t2, qc.mwpstartaddr1, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpstartaddr1, zero
+csrrs t2, 0x7D1, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpstartaddr1, zero
+
+csrrs t2, qc.mwpstartaddr2, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpstartaddr2, zero
+csrrs t2, 0x7D2, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpstartaddr2, zero
+
+csrrs t2, qc.mwpstartaddr3, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpstartaddr3, zero
+csrrs t2, 0x7D3, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpstartaddr3, zero
+
+csrrs t2, qc.mwpendaddr0, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x40,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpendaddr0, zero
+csrrs t2, 0x7D4, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x40,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpendaddr0, zero
+
+csrrs t2, qc.mwpendaddr1, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x50,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpendaddr1, zero
+csrrs t2, 0x7D5, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x50,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpendaddr1, zero
+
+csrrs t2, qc.mwpendaddr2, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x60,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpendaddr2, zero
+csrrs t2, 0x7D6, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x60,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpendaddr2, zero
+
+csrrs t2, qc.mwpendaddr3, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x70,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpendaddr3, zero
+csrrs t2, 0x7D7, zero
+// CHECK-ENC: encoding: [0xf3,0x23,0x70,0x7d]
+// CHECK-INST: csrrs t2, qc.mwpendaddr3, zero
diff --git a/llvm/test/MC/RISCV/xqciint-invalid.s b/llvm/test/MC/RISCV/xqciint-invalid.s
index 34da463cb49c9..4a94551d1d62f 100644
--- a/llvm/test/MC/RISCV/xqciint-invalid.s
+++ b/llvm/test/MC/RISCV/xqciint-invalid.s
@@ -108,3 +108,17 @@ qc.c.setint
# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension)
qc.c.setint x8
+
+
+# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction
+qc.c.mret x8
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension)
+qc.c.mret
+
+
+# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
+qc.c.mnret 10
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciint' (Qualcomm uC Interrupts Extension)
+qc.c.mnret
diff --git a/llvm/test/MC/RISCV/xqciint-valid.s b/llvm/test/MC/RISCV/xqciint-valid.s
index c05a402b5b14a..1ea41956396d5 100644
--- a/llvm/test/MC/RISCV/xqciint-valid.s
+++ b/llvm/test/MC/RISCV/xqciint-valid.s
@@ -79,3 +79,13 @@ qc.c.mileaveret
# CHECK-INST: qc.c.setint a0
# CHECK-ENC: encoding: [0x0a,0x15]
qc.c.setint x10
+
+
+# CHECK-INST: qc.c.mret
+# CHECK-ENC: encoding: [0x12,0x19]
+qc.c.mret
+
+
+# CHECK-INST: qc.c.mnret
+# CHECK-ENC: encoding: [0x92,0x19]
+qc.c.mnret
>From 9973d2e9731435e6c2b6717caa1f05419ca886c0 Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Tue, 18 Mar 2025 10:33:02 -0700
Subject: [PATCH 2/2] fixup! [RISCV] Xqciint SystemRegs, Final Assembly Insts
---
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 4 ++--
llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 --
llvm/test/MC/RISCV/xqciint-csrs-invalid.s | 6 ------
llvm/test/MC/RISCV/xqciint-csrs-valid.s | 14 --------------
4 files changed, 2 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index e1314d4fee8a0..06d434241f332 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -126,9 +126,9 @@ static const MCPhysReg FixedCSRFIMap[] = {
static constexpr uint64_t QCIInterruptPushAmount = 96;
static const std::pair<MCPhysReg, int8_t> FixedCSRFIQCIInterruptMap[] = {
- /* -1 is a gap for mepc/qc.mnepc */
+ /* -1 is a gap for mepc/mnepc */
{/*fp*/ FPReg, -2},
- /* -3 is a gap for mcause */
+ /* -3 is a gap for qc.mcause */
{/*ra*/ RAReg, -4},
/* -5 is reserved */
{/*t0*/ RISCV::X5, -6},
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 4c7db896e3380..842698e04e635 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -479,8 +479,6 @@ def : SysReg<"mctrctl", 0x34e>;
// Xqciint
let FeaturesRequired = [{ {RISCV::FeatureVendorXqciint} }], isRV32Only = 1 in {
def : SysReg<"qc.mmcr", 0x7C0>;
-def : SysReg<"qc.mnepc", 0x7C1>;
-def : SysReg<"qc.mncause", 0x7C2>;
def : SysReg<"qc.mntvec", 0x7C3>;
def : SysReg<"qc.mstktopaddr", 0x7C4>;
def : SysReg<"qc.mstkbottomaddr", 0x7C5>;
diff --git a/llvm/test/MC/RISCV/xqciint-csrs-invalid.s b/llvm/test/MC/RISCV/xqciint-csrs-invalid.s
index 02244e65194e1..a313ba4d52380 100644
--- a/llvm/test/MC/RISCV/xqciint-csrs-invalid.s
+++ b/llvm/test/MC/RISCV/xqciint-csrs-invalid.s
@@ -5,12 +5,6 @@
csrrs t2, qc.mmcr, zero
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mmcr' requires 'experimental-xqciint' to be enabled
-csrrs t2, qc.mnepc, zero
-// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mnepc' requires 'experimental-xqciint' to be enabled
-
-csrrs t2, qc.mncause, zero
-// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mncause' requires 'experimental-xqciint' to be enabled
-
csrrs t2, qc.mntvec, zero
// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mntvec' requires 'experimental-xqciint' to be enabled
diff --git a/llvm/test/MC/RISCV/xqciint-csrs-valid.s b/llvm/test/MC/RISCV/xqciint-csrs-valid.s
index ed6ac13d8a7a7..1e17974f5cb2c 100644
--- a/llvm/test/MC/RISCV/xqciint-csrs-valid.s
+++ b/llvm/test/MC/RISCV/xqciint-csrs-valid.s
@@ -12,20 +12,6 @@ csrrs t2, 0x7C0, zero
// CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7c]
// CHECK-INST: csrrs t2, qc.mmcr, zero
-csrrs t2, qc.mnepc, zero
-// CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c]
-// CHECK-INST: csrrs t2, qc.mnepc, zero
-csrrs t2, 0x7C1, zero
-// CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c]
-// CHECK-INST: csrrs t2, qc.mnepc, zero
-
-csrrs t2, qc.mncause, zero
-// CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7c]
-// CHECK-INST: csrrs t2, qc.mncause, zero
-csrrs t2, 0x7C2, zero
-// CHECK-ENC: encoding: [0xf3,0x23,0x20,0x7c]
-// CHECK-INST: csrrs t2, qc.mncause, zero
-
csrrs t2, qc.mntvec, zero
// CHECK-ENC: encoding: [0xf3,0x23,0x30,0x7c]
// CHECK-INST: csrrs t2, qc.mntvec, zero
More information about the llvm-commits
mailing list