[llvm] [AMDGPU] Fix a crash by skipping DBG instrs at start of sched region (PR #131167)

[Emma Pilkington via llvm-commits]

https://github.com/epilk updated https://github.com/llvm/llvm-project/pull/131167

>From 505b5dfb1a772f5f2bd82fcfa0f5c8ba16143656 Mon Sep 17 00:00:00 2001
From: Emma Pilkington <Emma.Pilkington at amd.com>
Date: Thu, 13 Mar 2025 08:29:49 -0400
Subject: [PATCH 1/2] [AMDGPU] Fix a crash by skipping DBG instrs at start of
 sched region

Fixes SWDEV-514946
---
 llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp   |  2 ++
 .../AMDGPU/dbg-value-starts-sched-region.mir  | 30 +++++++++++++++++++
 2 files changed, 32 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir

diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 5dcf523430fd2..80a8d7cc9e3b4 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -873,6 +873,8 @@ void GCNScheduleDAGMILive::computeBlockPressure(unsigned RegionIdx,
       Pressure[CurRegion] = RPTracker.moveMaxPressure();
       if (CurRegion-- == RegionIdx)
         break;
+      auto &Rgn = Regions[CurRegion];
+      NonDbgMI = &*skipDebugInstructionsForward(Rgn.first, Rgn.second);
     }
     RPTracker.advanceToNext();
     RPTracker.advanceBeforeNext();
diff --git a/llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir b/llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir
new file mode 100644
index 0000000000000..2fb9acf36bb5d
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir
@@ -0,0 +1,30 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s
+
+# Verify we maintain live-ins even if the first instruction in sched region is
+# DBG_.
+
+---
+name:            sched
+tracksRegLiveness: true
+registers:
+- { id: 1, class: sgpr_32, preferred-register: '', flags: [  ] }
+- { id: 2, class: sgpr_32, preferred-register: '', flags: [  ] }
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: sched
+    ; CHECK: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
+    ; CHECK-NEXT: S_NOP 0
+    ; CHECK-NEXT: SCHED_BARRIER 0
+    ; CHECK-NEXT: DBG_VALUE
+    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:sgpr_32 = COPY [[DEF]]
+    ; CHECK-NEXT: S_NOP 0
+    ; CHECK-NEXT: S_ENDPGM 0
+    %1:sgpr_32 = IMPLICIT_DEF
+    S_NOP 0
+    SCHED_BARRIER 0
+    DBG_VALUE
+    dead %2:sgpr_32 = COPY %1
+    S_NOP 0
+    S_ENDPGM 0
+...

>From 22d457fc18685c3a6830d930ec9fda188b041f98 Mon Sep 17 00:00:00 2001
From: Emma Pilkington <Emma.Pilkington at amd.com>
Date: Mon, 17 Mar 2025 09:36:11 -0400
Subject: [PATCH 2/2] address test comments

---
 .../CodeGen/AMDGPU/dbg-value-starts-sched-region.mir  | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir b/llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir
index 2fb9acf36bb5d..0785fe31d63b4 100644
--- a/llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir
+++ b/llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-misched -run-pass=machine-scheduler -o - %s | FileCheck %s
 
 # Verify we maintain live-ins even if the first instruction in sched region is
 # DBG_.
@@ -7,11 +7,8 @@
 ---
 name:            sched
 tracksRegLiveness: true
-registers:
-- { id: 1, class: sgpr_32, preferred-register: '', flags: [  ] }
-- { id: 2, class: sgpr_32, preferred-register: '', flags: [  ] }
 body:             |
-  bb.0.entry:
+  bb.0:
     ; CHECK-LABEL: name: sched
     ; CHECK: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
     ; CHECK-NEXT: S_NOP 0
@@ -20,11 +17,11 @@ body:             |
     ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:sgpr_32 = COPY [[DEF]]
     ; CHECK-NEXT: S_NOP 0
     ; CHECK-NEXT: S_ENDPGM 0
-    %1:sgpr_32 = IMPLICIT_DEF
+    %0:sgpr_32 = IMPLICIT_DEF
     S_NOP 0
     SCHED_BARRIER 0
     DBG_VALUE
-    dead %2:sgpr_32 = COPY %1
+    dead %1:sgpr_32 = COPY %0
     S_NOP 0
     S_ENDPGM 0
 ...