[llvm] [X86] Prevent APX NDD compression when it creates a partial write (PR #132051)

[Phoebe Wang via llvm-commits]

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@@ -6793,19 +6793,42 @@ static bool hasPartialRegUpdate(unsigned Opcode, const X86Subtarget &Subtarget,
 unsigned X86InstrInfo::getPartialRegUpdateClearance(
     const MachineInstr &MI, unsigned OpNum,
     const TargetRegisterInfo *TRI) const {
-  if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
+
+  // With the NDD/ZU features, ISel may generate NDD/ZU ops which
+  // appear to perform partial writes. We detect these based on flags
+  // and register class.
+  bool HasNDDPartialWrite = false;
+  if (OpNum == 0 && (Subtarget.hasNDD() || Subtarget.hasZU()) &&
+      X86II::hasNewDataDest(MI.getDesc().TSFlags)) {
+    Register Reg = MI.getOperand(0).getReg();
+    if (Reg.isVirtual()) {
+      auto &MRI = MI.getParent()->getParent()->getRegInfo();
+      if (auto *TRC = MRI.getRegClassOrNull(Reg))
+        HasNDDPartialWrite = (TRC->getID() == X86::GR16RegClassID ||
+                              TRC->getID() == X86::GR8RegClassID);
+    } else
+      HasNDDPartialWrite =
+          X86::GR8RegClass.contains(Reg) || X86::GR16RegClass.contains(Reg);
+  }
+
+  if (OpNum != 0 ||
+      !(HasNDDPartialWrite || hasPartialRegUpdate(MI.getOpcode(), Subtarget)))
     return 0;
 
-  // If MI is marked as reading Reg, the partial register update is wanted.
+  // For non-NDD ops, if MI is marked as reading Reg, the partial register
+  // update is wanted, hence we return 0.
+  // For NDD ops, if MI is marked as reading Reg, then it is possible to
+  // compress to a legacy form in CompressEVEX, which would create an
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phoebewang wrote:

I don't think we will mark the NDD dest as reading Reg given the NDD dest is purely a destination register. I think we probably don't have the knowledge if the source and dest will be the same register in the virtual register phase.

https://github.com/llvm/llvm-project/pull/132051