[llvm] [RISCV] Update some of the RVV memory ops in SiFive P400 & P600 sched models (PR #129575)

[Min-Yih Hsu via llvm-commits]

================
@@ -0,0 +1,316 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vlse8.v   v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vlse8.v   v8, (a0), t0
+vsetvli zero, zero, e8, mf8, ta, ma
+vlse8.v   v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vlse8.v   v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vlse8.v   v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vlse8.v   v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vlse8.v   v8, (a0), t0
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vlse16.v   v8, (a0), t0
+vsetvli zero, zero, e16, mf4, ta, ma
+vlse16.v   v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vlse16.v   v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vlse16.v   v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vlse16.v   v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vlse16.v   v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vlse32.v   v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vlse32.v   v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vlse32.v   v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vlse32.v   v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vlse32.v   v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vlse64.v   v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vlse64.v   v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vlse64.v   v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vlse64.v   v8, (a0), t0
+
+vsetvli zero, zero, e8, mf2, ta, ma
+vsse8.v   v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsse8.v   v8, (a0), t0
+vsetvli zero, zero, e8, mf8, ta, ma
+vsse8.v   v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vsse8.v   v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vsse8.v   v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vsse8.v   v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vsse8.v   v8, (a0), t0
+
+vsetvli zero, zero, e16, mf2, ta, ma
+vsse16.v   v8, (a0), t0
+vsetvli zero, zero, e16, mf4, ta, ma
+vsse16.v   v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vsse16.v   v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vsse16.v   v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vsse16.v   v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vsse16.v   v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsse32.v   v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vsse32.v   v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vsse32.v   v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vsse32.v   v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vsse32.v   v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsse64.v   v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vsse64.v   v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vsse64.v   v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vsse64.v   v8, (a0), t0
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      88
+# CHECK-NEXT: Total Cycles:      954
+# CHECK-NEXT: Total uOps:        88
+
+# CHECK:      Dispatch Width:    3
+# CHECK-NEXT: uOps Per Cycle:    0.09
+# CHECK-NEXT: IPC:               0.09
+# CHECK-NEXT: Block RThroughput: 472.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      1     1.00                  U     vsetvli	zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT:  1      22    8.00    *                   vlse8.v	v8, (a0), t0
----------------
mshockwave wrote:

Done

https://github.com/llvm/llvm-project/pull/129575